LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 137

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
6.3
A[7:5], END_SEL
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
nCS, nRD
Data Bus
A[4:1]
In this mode, performance is improved by allowing up to 8 DWORD read cycles, or 16 WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, END_SEL Setup to nCS, nRD valid
Address Stable to Data Valid
Address, END_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
t
asu
t
don
Figure 6.2 PIO Burst Read Cycle Timing
t
acyc
t
csdv
Table 6.4 PIO Burst Read Timing
DATASHEET
t
adv
t
acyc
137
t
adv
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
ah
TYP
t
doh
Revision 1.3 (02-23-10)
t
doff
t
csh
MAX
30
40
7
UNITS
ns
ns
ns
ns
ns
ns
ns