LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 83

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
5.1
5.2
5.2.1
RO
WO
R/W
R/WC
RC
LL
LH
SC
NASR
Reserved
Bits
Reserved
Registers
Default
States
SYMBOL
The LAN89218 contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data
FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs.
RX FIFO Ports
The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data. The RX Status FIFO has
two ports at different address locations. The RX Status FIFO Port causes the top of the RX Status
FIFO to be “popped”, and is destructive. The RX Status FIFO PEEK Port allows the top of the RX
Status FIFO to be read without “popping” it.
The RX Data FIFO has a single port; reading data from this port always causes the top of the RX Data
FIFO to be “popped”. This port is aliased to 8 DWORD (in 32-bit mode) or 16 DWORD locations (in
16-bit mode). The host may access the top of the RX Data FIFO through any of these locations.
Register Nomenclature and Access Attributes
RX and TX FIFO Ports
Read Only: If a register is read only, writes to this register have no effect.
Write Only: If a register is write only, reads always return 0.
Read/Write: A register with this attribute can be read and written
Read/Write Clear: A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Read to Clear: A register bit with this attribute is cleared when read.
Latch Low: Clear on read of register
Latch High: Clear on read of register
Self-Clearing
Not Affected by Software Reset
Certain bits within registers are listed as “Reserved”. Unless stated otherwise, these bits must be
written with zeros for future compatibility. The values of these bits are not guaranteed when read.
Certain configuration registers within the LAN89218 are listed as “Reserved”. These registers are not
guaranteed to return any particular value when read. These registers must not be written to or
modified by system failure; doing so could result in failure of the device and system.
At Reset - System reset, Software Reset, or POR - internal registers are set to their default states.
The default states provide a minimum level of functionality needed to successfully bring up a system,
but do not necessarily provide desired or optimal configuration of the device. It is the responsibility
of the system initialization software to properly determine the operating parameters and optional
system features that are applicable, and to program the LAN89218 registers accordingly.
DATASHEET
83
DESCRIPTION
Revision 1.3 (02-23-10)