DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 145
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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received with an incorrect HEC, HEC error monitoring transitions to the “Detection” state. In the “Detection” state,
good cells are passed on. Cells received with one or more errors are considered errored cells. If m cells are
received with a correct HEC or the data path cell boundary is updated, HEC error monitoring will transition to the
“Correction” state. The value of m is programmable (1, 2, 4, or 8). The HEC Error Monitoring state diagram is
shown in
HEC error monitoring will remain in the “Detection” state. If cell processing is disabled, HEC error monitoring will
not be performed.
Figure 10-28. HEC Error Monitoring State Diagram
HEC byte filtering discards the HEC byte. If HEC transfer is disabled in the receive system interface, the HEC byte
is extracted from the cell and discarded. The resulting 52-byte cell is then passed on for storage in the Receive
FIFO. If HEC transfer is enabled, the 53-byte cell is passed on for storage in the Receive FIFO. If cell processing is
disabled, HEC byte filtering will not be performed.
Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream
DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB
is in DT[7] of the outgoing FIFO data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit received.
Once all cell processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel
data stream and passed on to the Receive FIFO. Cells are stored in the Receive FIFO in a cell format. regardless
of whether or not they are transferred across a UTOPIA or POS-PHY interface. The cell format for a 53-byte cell
with a 32-bit bus is shown in
10-30.
Figure 10-29. Cell Format for 53-Byte Cell With 32-Bit Data Bus
Figure
Bit 31
C orrection
Payload 41
Payload 45
Payload 1
Payload 5
Header 1
HEC
10-28. HEC Error Monitoring starts in the “Correction” state. If header error correction is disabled,
•
•
•
Figure
Payload 42
Payload 46
Payload 2
Payload 6
Header 2
00h
10-29. The cell format for a 52-byte cell with a 32-bit bus is shown in
•
•
•
cell boundary update
m th good cell
corrected cell
errored cell
Payload 43
Payload 47
Payload 3
Payload 7
Header 3
00h
145
•
•
•
D etection
Payload 44
Payload 48
Payload 4
Payload 8
Header 4
00h
•
•
•
Bit 0
13
14
2
3
1
4
nd
rd
st
th
th
th
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Figure
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