DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 78

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-29. UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer
8.3.5.2
Figure 8-30
indicate to the ATM device that they can accept cell data by asserting the TDXA[n]. On clock edge 2, the ATM
device selects PHY port '1' by putting address ‘00h’ on the address bus. On clock edge 5, the ATM device starts a
cell transfer to PHY port '1' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to
indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts TSOX as it continues to
place additional bytes of the cell on TDATA. On clock edge 13, PHY port ‘2’ asserts TDXA[2] to indicate it is ready
to accept a cell. On clock edge 15, PHY port ‘1’ deasserts TDXA[1] to indicate to the ATM device that it does not
have the availability to receive another complete cell. On clock edge 16, the ATM device selects PHY port '2' by
deasserting TEN and placing PHY port '2's address on TADR. On clock edge 17, the ATM device starts the transfer
of a cell to PHY port '2' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to
indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues
to place additional bytes of the cell on TDATA.
Figure 8-30. UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode
TDXA[2]
TDXA[1]
TDXA[3]
TDXA[4]
TDATA
TSCLK
Cell From:
TADR
Transfer
Cell To:
TSOX
Transfer
RADR
RDAT
TEN
RCLK
RPXA
RSOX
REN*
UTOPIA Level 3 Functional Timing
shows a multiport transmit-interface multiple cell transfer to different PHY devices. PHY port '1', ‘3’, ‘4’
L
1
P45
1
1F
L
2
P46
N
2
M
3
3
P47
1F
M
4
4
P48
N
5
H1
5
1F
N
X
6
H2
6
N
H1
O
7
H3
7
1F
O
…
8
00h
8
N
9
P42
9
78
1F
N
10
PORT 1
P43
10
H2
P
11
P44
11
H3
1F
P
12
P45
12
H4
L
13
P46
13
1F
P1
L
14
P47
14
P2
M
15
P48
15
N
1F
P3
M
16
16
P4
O
17
H1
17
1F
P5
O
01h
18
PORT 2
H2
18
P6
P
19
H3
19
1F
P7
P
20
H4
20
P8
L