DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 72
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 8-18
Figure 8-18. E3 G.751 PLCP Transmit Overhead Port Timing
8.3.3
The fractional overhead pins provide the ability to insert bits in the DS3/E3 payload that are not used for cells or
packets. The source of fractional overhead bits is controlled by an internal register (see FRAC.TCR), specifying
internal generation or external sourcing via the TFOHENIn pin. The allocation of DS3/E3 payload used for cell and
packet data is also programmable or controlled by the TFOHENIn pin. The TSOFIn, TSOFOn, TDENn, RSOFOn
and RDENn pins are used to determine which bit positions are DS3/E3 overhead so that fractional overhead bits
will be inserted only in DS3/E3 payload. The TCLKOn and RCLKOn clocks can be configured for gapped modes
that will toggle for each fractional overhead bit, allowing a simple way of using the overhead bits for messaging.
Figure 8-19
fractional overhead, and L designates DS3/E3 overhead, based on TDEN.
Figure 8-19. External (XFRAC) Transmit Fractional Timing
Figure 8-20
Figure 8-20. External (XFRAC) Receive Fractional Timing
TPOHSOF
TPOHCLK
TPOHEN
RFOHENI
RCLKI or
TFOHENI
TCLKI or
RCLKO
TPOH
RDEN
TCLKO
TSOFO
RSER
RSOF
TSOFI
TFOH
TDEN
Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing
shows the relationship of the E3 G.751 PLCP transmit-overhead port pins.
shows the timing with the external fractional transmit port pins. P designates payload bits, F designates
shows the timing with the external fractional receive port pins.
1
C1
6
1
PY4
PX5
PX5
1
2
C1
7
2
PY5
PX6
PX6
2
3
C1
8
3
PY6
PY3
FX1
3
4
Z3
1
4
FY1
PY4
FX2
4
5
Z3
2
5
PY5
FY2
FX3
5
6
Z3
3
6
PY6
FY3
6
L1
L1
7
Z3
4
7
P11
P11
7
L1
8
Z3
5
8
P11
P12
P12
8
9
Z3
6
9
P12
P13
P13
9
10
Z3
7
10
10
P13
P14
P14
L1
11
Z3
8
72
11
11
P14
P11
P15
P15
12
Z2
1
12
12
P15
P12
P16
P15
13
Z2
2
13
13
P13
P16
F11
14
Z2
3
14
14
P14
F11
F12
15
Z2
4
15
15
P15
F12
F13
16
Z2
5
16
16
F13
P16
L2
L2
17
Z2
6
17
17
L2
P21
P21
18
Z2
7
18
18
P21
P22
P22
19
Z2
8
19
19
P22
P23
P23
20
Z1
1
20
20
P23
P24
P24
L2
21
Z1
2
21
21
P21
P24
P25
P25
22
Z1
3
22
22
P25
P22
P26
P26
23
Z1
4
23
23
P26
P23
F21
24
Z1
5
24
24
F21
F22
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