DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 150
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.8 DS3/E3 PLCP Framer
10.8.1 General Description
The PLCP Framer demaps the ATM cells from the DS3/E3 PLCP data stream in the receive direction and maps
ATM cells into the DS3/E3 PLCP data stream in the transmit direction.
The receive direction extracts the PLCP frame from the DS3/E3 data stream, performs frame processing, and
outputs the cells with a beginning of cell indication via the payload interface.
The transmit direction inputs the cells via the payload interface, generates the frame, and inserts the PLCP frame
into the DS3/E3 data stream. See
Figure 10-31. PLCP Framer Functional Diagram
10.8.2 Features
•
•
•
•
•
•
•
Clock Rate
DS3 PLCP frame ATM cell extraction and insertion – Accepts a DS3 payload and performs DS3 PLCP
overhead termination and generation.
E3 PLCP frame ATM cell extraction and insertion – Accepts a G.751 E3 payload and performs E3 PLCP
overhead termination and generation.
Generates and detects alarms and errors – In the receive direction, PLCP alarm conditions (OOF, LOF,
COFA, and RAI) and errors (framing, parity, and REI) are detected on the receive signal. In the transmit
direction, alarm conditions and errors can be inserted into the transmit data stream.
Receive overhead extraction port – Extracts all PLCP overhead from the receive signal and outputs it on a
serial interface (RPOH pin).
Externally controlled transmit overhead insertion port – Can insert all PLCP overhead into the transmit
signal from a serial interface. Overhead insertion is fully controlled via the serial overhead interface (TPOH,
TPOHEN, TPOHSOF, TPOHCLK).
Full Duplex serial HDLC channel extraction/insertion – An HDLC channel can be extracted from and/or
inserted into the F1, M1, M2, or M1 and M2 bytes in the PLCP data stream.
Full Duplex serial Trail Trace extraction/insertion – A trail trace can be extracted from and/or inserted into
the F1 byte in the PLCP data stream.
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
Figure 10-31
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Receive
Framer
Formatter
DS3 / E3
Transmit
Buf f er
Trace
Trail
for the location of the PLCP framer in the DS318x devices.
HDLC
UA1
GEN
150
TX FRAC/
PLCP
RX FRAC/
PLCP
Processor
Processor
Rx Packet
Processor
Processor
Tx Packet
RX BERT
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
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