DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 322
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 13: Remote Error Indication Latched (REIL) – This bit is set when a far-end block error is detected.
Bit 12: Parity Error Latched (PEL) – This bit is set when a BIP-8 parity error is detected.
Bit 11: Framing Error Latched (FEL) – This bit is set when a framing error is detected.
Bit 8: Loss Of Frame Change Latched (LOFL) – This bit is set when the LOF bit changes state.
Bit 5: Remote Error Indication Count Latched (REICL) – This bit is set when the REIC bit transitions from zero
to one.
Bit 4: Parity Error Count Latched (PECL) – This bit is set when the PEC bit transitions from zero to one.
Bit 3: Framing Error Count Latched (FECL) – This bit is set when the FEC bit transitions from zero to one.
Bit 2: Remote Defect Indication Change Latched (RAIL) – This bit is set when the RAI bit changes state.
Bit 1: Change Of Frame Alignment Latched (COFAL) – This bit is set when the data path frame counters are
updated with a new frame alignment that is different from the previous frame alignment.
Bit 0: Out Of Frame Change Latched (OOFL) – This bit is set when the OOF bit changes state.
15
—
—
7
14
—
—
6
PLCP.RSRL1
PLCP Receive Status Register Latched 1
(1,3,5,7)68h
REICL
REIL
13
5
PECL
PEL
12
4
322
FECL
FEL
11
3
RAIL
10
—
2
COFAL
—
9
1
OOFL
LOFL
8
0
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