DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 36
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.10 Clear-Channel Octet Aligned ATM/Packet—OHM Mode
The Clear-Channel Octet Aligned ATM/Packet—OHM Mode maps/demaps ATM cells or HDLC packets into/from a
serial datastream, bypassing both the DS3/E3 formatter/framer and the LIU, supporting arbitrary framing modes.
Major functional blocks for the Clear-Channel Octet Aligned ATM/Packet—OHM Mode are shown in
Mapping configuration is programmable on per-port basis and is shown in
Table 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode Configuration
Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode
TOHMOn
TLCLKn
RLCLKn
ROHMIn
TOHMIn
TDATn
RDATn
MODE
Clock Rate
Adapter
TUA1
FM[5:0]
1XX011
1XX011
1XX011
1XX011
1XX011
1XX011
IEEE 1149.1
Access Port
JTAG Test
SIM[1:0]
GL.CR1
00
01
10
11
10
11
GEN
UA1
PORT.CR2
PMCPE
36
X
X
1
1
0
0
Parallel to
Serial to
Parallel
Serial
Table
RX BERT
Tx Packet
Processor
TX BERT
Rx Packet
Processor
Processor
6-10.
Processor
Tx Cell
Rx Cell
Microprocessor
Interface
FIFO
Tx
FIFO
Rx
Interface
n = port # (1-4)
System
Figure
6-10.
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