DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 351
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address/Type:
Bit #
Name
Default
Bit #
Name
Default
Bit 11: Out Of Sync Change Interrupt Enable (OOSIE) – This bit enables an interrupt if the OOSL bit in the
CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 10: Change Of Cell Delineation Interrupt Enable (COCDIE) – This bit enables an interrupt if the COCDL bit
in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 9: Out Of Cell Delineation Change Interrupt Enable (OCDCIE) – This bit enables an interrupt if the OCDCL
bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 8: Loss Of Cell Delineation Change Interrupt Enable (LCDCIE) – This bit enables an interrupt if the LCDCL
bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 7: Receive Errored Header Cell Interrupt Enable (RECIE) – This bit enables an interrupt if the RECL bit in
the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 6: Receive Corrected Header Cell Interrupt Enable (RCHIE) – This bit enables an interrupt if the RCHL bit in
the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 5: Receive Idle Cell Detection Interrupt Enable (RIDIE) – This bit enables an interrupt if the RIDL bit in the
CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 4: Receive Unassigned Cell Detection Interrupt Enable (RUDIE) – This bit enables an interrupt if the RUDL
bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 3: Receive Invalid Cell Detection Interrupt Enable (RIVDIE) – This bit enables an interrupt if the RIVDL bit in
the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Receive Errored Header Cell Count Interrupt Enable (RECCIE) – This bit enables an interrupt if the
RECCL bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RECIE
15
—
0
7
0
RCHIE
14
—
0
6
0
CP.RSRIE
Cell Processor Receive Status Register Interrupt Enable
(1,3,5,7)D2h
RIDIE
13
—
0
5
0
RUDIE
12
—
0
0
4
351
RIVDIE
OOSIE
11
0
3
0
COCDIE
RECCIE
10
0
2
0
OCDCIE
RHPCIE
9
0
1
0
RCHCIE
LCDCIE
8
0
0
0
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