COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 23

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
SMSC COM20022I 3V
Read/Write
Read/Write
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet.
The basic sequence of operation is as follows:
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
The following sequences show the data transfer for a DMA read and a DMA write. The transfer of data
between system memory and internal RAM functions as a memory to I/O DMA transfer. Since it is treated
as an I/O device, the COM20022I 3V has to create the RAM address. Therefore the COM20022I 3V’s
address pointers must be programmed before starting the DMA transfers.
Signal
Signal
nDACK
nDACK
DREQ
DREQ
nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=
“1”).
DREQ becomes inactive after TC asserts (when nDACK= “0”). In this case, DREQ doesn't become
active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ= 0 and the present cycle finishes.
TC
TC
Figure 5.6
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing
- Burst Mode DMA Data Transfer Rough Timing
DATASHEET
Page 23
Revision 02-27-06