COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 70

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 02-27-06
nIOCS16
D0-D15
A0-A2
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
nCS
nDS
*
***: nCS may become active after control becomes active, but the data setup time will now
****: t12 is measured from the latest active (valid) timing among nCS, A0-A2.
*****:
Note 1:
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
Note 2 is applied to an access to Data Register by DMA transfer.
DIR
t10
t11
t12
t13
T
T
T
T
t1
t2
t3
t4
t5
t6
t7
t8
t9
ARB
ARB
ARB
opr
be 30 nS measured from the later of nCS falling or Valid Data available.
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
Write cycle for Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5T
the leading edge of the next nDS.
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
requires a minimum of 4T
of the next nDS.
should be doubled when considering back-to-back COM20022 cycles.
opr
if SLOW ARB = 1
Parameter
opr
t1
if SLOW ARB = 0
to Next Time
CASE 1: BUSTMG pin = HIGH
t5
t3
DATASHEET
t12
ARB
from the trailing edge of nDS to the leading edge
)**
Page 70
VALID
ARB
t10
from the trailing edge of nDS to
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
VALID DATA
VALID VALUE
4T
30***
0*****
t8
min
15
10
10
10
10
20
20
ARB
5
0
*
40****
max
t9
t2
t7
Note 2
t4
t11
t6**
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t13
t6
SMSC COM20022I 3V
Datasheet