COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 35

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Note 6.3
6.2.14 Bus Control Register
SMSC COM20022I 3V
nWR/nRD
nREFEX
the 20 MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU
bus support. The EF bit is used to enable the new timing for certain functions in the COM20022I 3V (if EF
= 0, the timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to
enable the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM
initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence
to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benefit of shortened network reconfiguration periods. The time periods shown
in the table following are limited by a maximum number of nodes in the network. These time-out period
values are for 10Mbps. For other data rates, scale the time-out period time values accordingly; the
maximum node count remains the same.
The Bus Control Register is new to the COM20022I 3V. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register).
This register contains bits for control of the DMA functionality. The DRQPOL bit is used to set the active
polarity of the DREQ pin. The TCPOL bit is used to set the active polarity of TC pin.
The DMAMD[0,1] bits select the data transfer mode of the DMA, either non-burst, burst, Programmable-
Burst by timer or programmable burst by cycle counter.
This transfer mode influences to the timing the DREQ pin. The use of the ITCEN/RTRG bit transfer mode
dependent. ITCEN is the Internal Terminal Counter Enable. It is used to select whether the DMA is
terminated by external TC or by either internal or external TC. ITCEN is for Non-Burst or Burst mode.
RTRG selects the re-trigger mode as either external or internal. It is for the two Programmable-Burst
modes. If RTRG = 0, the deasserted DREQ pin is reasserted on the falling edge of the nREFEX pin. If
RTRG = 1, the deasserted DREQ pin is reasserted by the timeout of the internal timer (350 ns or 750 ns,
as selected by the GTTM bit.) See Figure 6.1 following.
nDACK
DREQ
The node ID value 255 must exist in the network for the 13.125 mS time-out to be valid.
RCNTM1
0
0
1
1
Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing
RTRG=0
RCNTM0
0
1
0
1
DATASHEET
210 mS
52.5 mS
26.25 mS
13.125 mS
TIME-OUT PERIOD
Page 35
(Note 6.3)
nWR/nRD
nDACK
DREQ
Up to 255 nodes
Up to 64 nodes
Up to 32 nodes
Up to 16 nodes
MAX NODE COUNT
RTRG=1
350/750ns
(Note 6.3)
Revision 02-27-06