COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 68

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 02-27-06
Figure 8.9
nIOCS16
D0-D15
**
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
A0-A2
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
*
***:
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
*****
nWR
nRD
nCS
T
T
T
T
t1
t5
t2
t3
t4
t6
t7
t8
t9
t10
t11
t12
ARB
ARB
ARB
opr
be 30 nS measured from the later of nCS falling or Valid Data available.
nCS may become active after control becomes active, but the data setup time will now
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Register requires a minimum of 5T
leading edge of nWR.
requires a minimum of 4T
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5T
leading edge of the next nWR.
Address Setup to nWR Active
Address Hold from nWR Inactive
nCS Setup to WR Active
nCS Hold from nWR Inactive
Cycle Time (nWR
Valid Data Setup to nWR High
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
- Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
opr
to nWR Low
if SLOW ARB = 1
Parameter
Note 3
opr
t10
t1
if SLOW ARB = 0
CASE 1: BUSTMG pin = HIGH
t3
to Next
DATASHEET
t11
ARB
from the trailing edge of nWR to the leading edge
ARB
ARB
)**
Page 68
VALID
from the trailing edge of nWR to the
from the trailing edge of nRD to the
t8
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
VALID DATA
VALID VALUE
4T
0*****
t6
30***
min
15
10
10
20
20
20
ARB
5
0
*
40****
max
t7
t2
Note 2
t4
t9
t5**
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t12
t5
SMSC COM20022I 3V
Datasheet