SCC2692AC1A44 NXP Semiconductors, SCC2692AC1A44 Datasheet

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SCC2692AC1A44

Manufacturer Part Number
SCC2692AC1A44
Description
UART 2-CH 5V 44-Pin PLCC Tube
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SCC2692AC1A44

Package
44PLCC
Number Of Channels Per Chip
2
Maximum Data Rate
0.1152 MBd
Transmitter And Receiver Fifo Counter
No
Operating Supply Voltage
5 V
Minimum Single Supply Voltage
4.5 V
Maximum Processing Temperature
245 °C
Maximum Supply Current
10 mA

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Philips
Semiconductors
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
INTEGRATED CIRCUITS
1998 Sep 04

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SCC2692AC1A44 Summary of contents

Page 1

... SCC2692 Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1998 Feb 19 IC19 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1998 Sep 04 ...

Page 2

... Power down mode Receiver timeout mode Commercial and industrial temperature range versions TTL compatible Single +5V power supply COMMERCIAL INDUSTRIAL V = +5V +10 +5V +10 + - SCC2692AC1N40 SCC2692AE1N40 SCC2692AC1N28 SCC2692AE1N28 SCC2692AC1A44 SCC2692AE1A44 SCC2692AC1B44 SCC2692AE1B44 2 Product specification SCC2692 DWG # SOT129-1 SOT117-1 SOT187-2 SOT307–2 853–0895 19971 ...

Page 3

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART IP3 2 39 IP4 IP5 A0 1 IP1 4 37 IP6 IP2 CEN A3 4 IP0 7 34 RESET WRN 5 WRN RDN 6 RDN 9 32 X1/CLK RxDB 7 RxDB 10 31 RxDA DIP TxDB 8 TxDB 11 30 TxDA OP1 9 OP1 12 29 OP0 D1 10 OP3 ...

Page 4

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM 8 D0–D7 BUS BUFFER OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 4 A0–A3 R/W CONTROL RESET INTERRUPT CONTROL INTRN IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER X1/CLK XTAL OSC X2 CSRA ...

Page 5

... DUART and the CPU the least significant bit. CEN Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines in the 3-State condition. WRN X ...

Page 6

... Test conditions for outputs 150pF, except interrupt outputs. Test conditions for interrupt outputs All outputs are disconnected. Inputs are switching between CMOS levels > < See UART application note for CHARACTERISTICS SYMBOL SYMBOL Reset Timing (See Figure 3) t RESET pulse width RES 5 ...

Page 7

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) AC CHARACTERISTICS (Continued) SYMBOL SYMBOL 5 Port Timing (See Figure 5) Port input setup time before RDN Low Port input hold time after RDN High output valid from WRN High PD n Interrupt Timing (See Figure 6) INTRN (or OP3-OP7 when used as interrupts) negated from: ...

Page 8

... X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART external clock is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 7. ...

Page 9

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) conditions of the UART. When this 8-bit port is used as a general purpose output, the pins so defined will assume the compliment of the associated bit in the Output Port Register (OPR). OPR( results in OP(n) = Low and vice versa. Bits of the OPR can be individually set and reset. A bit is set by performing a write operation at address H’ ...

Page 10

... ISR will show the “Counter Ready” bit not set. If nothing else is interrupting, this read of the ISR will return a x’00 character. Multidrop Mode The DUART is equipped with a receiver wake-up mode for multidrop applications. This mode is selected by programming bits MR1A[4:3] or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of operation, a ‘ ...

Page 11

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 1. SCC2692 Register Addressing See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication Table 2. Register Bit Formats ...

Page 12

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats (Continued) BIT 7 BIT 6 RECEIVED FRAMING SRA BREAK* ERROR* SRB SRB Yes 1 = Yes NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “ ...

Page 13

... MR1A. Accesses to MR2A do not change the pointer. MR2A[7:6] – Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7: the normal mode, with the transmitter and receiver operating independently. MR2A[7: places the channel in the automatic echo mode, which automatically re-transmits the received data ...

Page 14

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1. Received data is re-clocked and retransmitted on the TxDA out- put. 2. The receive clock is used for the transmitter. 3. Received data is not sent to the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not regenerated for transmission, i ...

Page 15

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) MR1B – Channel B Mode Register 1 MR1B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR1 by RESET ‘set pointer’ command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B. ...

Page 16

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1110 Power Down Mode On. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires a X1/CLK. While in the power down mode, do not issue any commands to the CR except the disable power down mode command ...

Page 17

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) OPCR – Output Port Configuration Register OPCR[7] – OP7 Output Select This bit programs the OP7 output to provide one of the following: 0 The complement of OPR[7]. 1 The Channel B transmitter interrupt output which is the complement of TxRDYB. When in this mode OP7 acts as an open- drain output ...

Page 18

... ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 00 when the DUART is reset. 16 ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0] ...

Page 19

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) data clock. The formula for calculating the divisor n to load to the CTUR and CTLR for a particular 1X data clock is shown below: counter clock frequency baud rate desired Often this division will result in a non-integer number; 26.3, for example ...

Page 20

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) A0– CEN t CS RDN D0–D7 FLOAT (READ WDN D0–D7 (WRITE) RDN IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 1998 Sep RWD NOT VALID FLOAT VALID t RWD VALID Figure 4. Bus Timing OLD DATA Figure 5. Port Timing ...

Page 21

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) WRN INTERRUPT OUTPUT RDN INTERRUPT OUTPUT NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal point 0.5V above V ...

Page 22

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TxC (INPUT) TxD TxC (1X OUTPUT) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) WRN CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 1998 Sep 04 1 BIT TIME ( CLOCKS) t TXD ...

Page 23

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP5) RDN STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR( and MR( MASTER STATION ADD#1 TxD TRANSMITTER ENABLED TxRDY (SR2) WRN MR1(4– ...

Page 24

... Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” ...

Page 25

... A condition that occurs infrequently has been observed where the receiver will ignore all data caused by a corruption of the start bit generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to continue to function properly. ...

Page 26

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 Sep 04 26 Product specification SCC2692 SOT129-1 ...

Page 27

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP28: plastic dual in-line package; 28 leads (600 mil) 1998 Sep 04 27 Product specification SCC2692 SOT117-1 ...

Page 28

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 1998 Sep 04 28 Product specification SCC2692 SOT187-2 ...

Page 29

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 1998 Sep 04 29 Product specification SCC2692 SOT307-2 ...

Page 30

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. ...

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