SCC2692AC1A44 NXP Semiconductors, SCC2692AC1A44 Datasheet - Page 11

• Manufacturer Part Number: SCC2692AC1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2692AC1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.5 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA

Philips Semiconductors
Table 1. SCC2692 Register Addressing
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
Table 2. Register Bit Formats
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
1998 Sep 04
NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
Dual asynchronous receiver/transmitter (DUART)
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MR1A
MR1A
MR1B
MR2A
MR2A
MR2B
CSRA
CSRA
CSRB
CSRB
CRA
CRB
CRB
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BIT 7
CONTROL
RxRTS
0 = No
1 = Yes
BIT 7
BIT 7
BIT 7
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MISCELLANEOUS COMMANDS
See Text and Timing Requirement
RECEIVER CLOCK SELECT
BIT 6
0 = RxRDY
1 = FFULL
A0
SELECT
BIT 6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RxINT
BIT 6
BIT 6
See Text
BIT 5
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
BRG Test
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
1X/16X Test
Rx Holding Register B (RHRB)
Reserved
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
BIT 5
0 = Char
1 = Block
CONTROL
ERROR
MODE*
0 = No
1 = Yes
BIT 5
TxRTS
BIT 5
READ (RDN = 0)
BIT 4
BIT 4
11
BIT 4
ENABLE Tx
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
PARITY MODE
0 = No
1 = Yes
BIT 4
DISABLE Tx
CTS
0 = No
1 = Yes
BIT 3
BIT 3
BIT 3
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
BIT 3
ENABLE Tx
TRANSMITTER CLOCK SELECT
0 = No
1 = Yes
BIT 2
0 = Even
BIT 2
PARITY
1 = Odd
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Reserved
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
TYPE
BIT 2
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
BIT 2
STOP BIT LENGTH*
See Text
WRITE (WRN = 0)
DISABLE Rx
0 = No
1 = Yes
BIT 1
BIT 1
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
BIT 1
BIT 1
CHARACTER
Product specification
SCC2692
BITS PER
00 = 5
01 = 6
10 = 7
11 = 8
ENABLE Rx
BIT 0
C = 1.813
D = 1.875
E = 1.938
F = 2.000
0 = No
1 = Yes
BIT 0
BIT 0
BIT 0