SCC2692AC1A44 NXP Semiconductors, SCC2692AC1A44 Datasheet - Page 7

• Manufacturer Part Number: SCC2692AC1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2692AC1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.5 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA

1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
3. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
7. Guaranteed by characterization of sample units.
8. Minimum frequencies are not tested but are guaranteed by design.
9. 325ns maximum for T
10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.
Philips Semiconductors
AC CHARACTERISTICS (Continued)
NOTES:
1998 Sep 04
SYMBOL
SYMBOL
t
t
t
t
t
f
t
f
t
f
t
f
t
t
t
t
PS
PH
PD
IR
CLK
CLK
CTC
CTC
RX
RX
TX
TX
TXD
TCS
RXS
RXH
Dual asynchronous receiver/transmitter (DUART)
Port Timing
Interrupt Timing (See Figure 6)
Clock Timing (See Figure 7)
Transmitter Timing (See Figure 8)
Receiver Timing (See Figure 9)
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
be negated for t
9
9
9
9
8
8
10
8
5
Port input setup time before RDN Low
Port input hold time after RDN High
OP
INTRN (or OP3-OP7 when used as interrupts) negated from:
X1/CLK High or Low time
X1/CLK frequency
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time
RxC frequency
TxC High or Low time
TxC frequency
TxD output delay from TxC external clock input on IP pin
Output delay from TxC low at OP pin to TxD data output
RxD data setup time before RxC high at external clock input on IP pin
RxD data hold time after RxC high at external clock input on IP pin
(See Figure 5)
n
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
RWD
output valid from WRN High
to guarantee that any status register changes are valid.
A
> 70 C.
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
(16X)
(16X)
(1X)
(1X)
1, 2, 4
PARAMETER
PARAMETER
7
Min
100
100
220
220
240
200
0
0
0
0
0
0
0
0
0
L
= 50pF, R
LIMITS
3.6864
Typ
3
L
= 2.7K to V
Product specification
Max
400
300
300
300
300
300
300
350
150
SCC2692
4
4
2
1
1
1
CC
UNIT
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns