SCC2692AC1A44 NXP Semiconductors, SCC2692AC1A44 Datasheet - Page 5

• Manufacturer Part Number: SCC2692AC1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2692AC1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.5 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA

Philips Semiconductors
PIN DESCRIPTION
1998 Sep 04
SYMBOL
SYMBOL
X1/CLK
RESET
INTRN
Dual asynchronous receiver/transmitter (DUART)
D0-D7
A0-A3
RxDA
RxDB
TxDA
TxDB
WRN
RDN
GND
CEN
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
V
IP0
IP1
IP2
IP3
IP4
IP5
IP6
X2
CC
APPLICABLE
40,44
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
28
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TYPE
TYPE
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the
D0-D7 lines in the 3-State condition.
Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in
the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected although it is permissible to ground it.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output
is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an
internal V
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an
internal V
Input 2: General purpose input or counter/timer external clock input. Pin has an internal V
device supplying 1 to 4 mA of current.
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
Power Supply: +5V supply input.
Ground
CC
CC
CC
CC
pull-up device supplying 1 to 4 mA of current.
pull-up device supplying 1 to 4 mA of current.
pull-up device supplying 1 to 4 mA of current.
pull-up device supplying 1 to 4 mA of current.
CC
CC
pull-up device supplying 1 to 4 mA of current.
5
pull-up device supplying 1 to 4 mA of current.
NAME AND FUNCTION
NAME AND FUNCTION
Product specification
SCC2692
CC
pull-up