SCC2692AC1A44 NXP Semiconductors, SCC2692AC1A44 Datasheet - Page 24

• Manufacturer Part Number: SCC2692AC1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2692AC1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.5 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA

is driven high, the transmitter will stop sending data at the end of the
Philips Semiconductors
Output Port Notes
The output ports are controlled from four places: the OPCR register,
the OPR register, the MR registers and the command register. The
OPCR register controls the source of the data for the output ports
OP2 through OP7. The data source for output ports OP0 and OP1 is
controlled by the MR and CR registers. When the OPR is the source
of the data for the output ports, the data at the ports is inverted from
that in the OPR register. The content of the OPR register is
controlled by the “Set Output Port Bits Command” and the “Reset
Output Bits Command”. These commands are at E and F,
respectively. When these commands are used, action takes place
only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the “Set Output Port Bits”
command will result in OPR5 being set to one. The OP5 would then
be set to zero (V
word associated with the “Reset Output Ports Bits” command would
set OPR5 to zero and, hence, the pin OP5 to a one (V
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal
is active low; thus, it is called CTSAN for TxA and CTSBN for TxB.
RTS is usually meant to be a signal from the receiver indicating that
the receiver is ready to receive data. It is also active low and is,
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin
OP0 and RTSBN is on OP1. A receiver’s RTS output will usually be
connected to the CTS input of the associated transmitter. Therefore,
one could say that RTS and CTS are different ends of the same
wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input
present character being serialized. It is usually the RTS output of the
receiver that will be connected to the transmitter’s CTS input. The
receiver will set RTS high when the receiver FIFO is full AND the
start bit of the fourth character is sensed. Transmission then stops
with four valid characters in the receiver. When MR2(4) is set to one,
CTSN must be at zero for the transmitter to operate. If MR2(4) is set
to zero, the IP pin will have no effect on the operation of the
transmitter.
MR1(7) is the bit that allows the receiver to control OP0. When OP0
(or OP1) is controlled by the receiver, the meaning of that pin will be
RTS. However, a point of confusion arises in that OP0 (or OP1) may
also be controlled by the transmitter. When the transmitter is
controlling this pin, its meaning is not RTS at all. It is, rather, that the
transmitter has finished sending its last data byte. Programming the
OP0 or OP1 pin to be controlled by the receiver and the transmitter
at the same time is allowed, but would usually be incompatible.
1998 Sep 04
OP0–OP7
Dual asynchronous receiver/transmitter (DUART)
TxDA/B
D0–D7
INTRN
Figure 13. Test Conditions on Outputs
SS
). Similarly, a one in bit position 5 of the data
50pF
150pF
2.7K
750
DD
).
SD00143
+5V
2.15V
24
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the OP0 or OP1 pin which
is still an output port. Therefore, the state of OP0 or OP1 should be
set low (either by commands of the CR register or by writing to the
Set Output Ports Register) for the receiver to generate the proper
RTS signal. The logic at the output is basically a NAND of the OPR
register and the RTS signal as generated by the receiver. When the
RTS flow control is selected via the MR(7) bit state of the OPR
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the OP0 or OP1 pins to the control of
the OPR register.
Transmitter Disable Note
The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode or one bit time in the 1x mode. Also, if the transmitter,
while in the enabled state and underrun condition, is immediately
disabled after a single character is loaded to the transmit holding
register, that character will not be sent.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
(TxEMT is always set if the transmitter has underrun or has just
been enabled), be sure the TxRDY bit is active immediately before
issuing the transmitter disable instruction. TxRDY sets at the end of
the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Table 6. Baud Rates Extended
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode.
When in the BRG test mode, the baud rates change as shown to the
left. This change affects all receivers and transmitters on the DUART.
See “Extended baud rates for SCN2681, SCN68681, SCC2691,
SCC2692, SCC68681 and SCC2698B” in application notes
elsewhere in this publication
The test mode at address H‘A’ changes all transmitters and
receivers to the 1x mode and connects the output ports to some
internal nodes.
CSR[7:4]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
38.4K
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
200
300
600
110
50
Normal BRG
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
19.2K
Timer
134.5
1,200
2,000
2,400
4,800
1,800
9,600
110
150
300
600
75
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
115.2K
19.2K
28.8K
57.6K
57.6K
57.6K
38.4K
4,800
1,076
1,050
4,800
9,600
Timer
880
Product specification
SCC2692
BRG Test
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
115.2K
7,200
1,076
14.4K
28.8K
57.6K
2,000
57.6K
4,800
14.4K
9,600
19.2K
Timer
880