MT46V64M8P-5B:F Micron Technology Inc, MT46V64M8P-5B:F Datasheet - Page 37

• Manufacturer Part Number: MT46V64M8P-5B:F
• Description: DRAM Chip DDR SDRAM 512M-Bit 64Mx8 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M8P-5B:F

• Density: 512 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 64Mx8
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 195mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Derating Data Valid Window (
30. The input capacitance per pin group will not differ by more than this maximum
31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially).
32. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/
33. V
34. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
35.
36. READs and WRITEs with auto precharge are not allowed to be issued until
37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV
38. Normal output drive curves:
38b. The driver pull-down current variation, within nominal voltage and temperature
38a. The full driver pull-down current variation from MIN to MAX process; tempera-
amount for any given device.
DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added
to
-6T speed grades, the slew rate must be ≥0.5 V/ns. If the slew rate exceeds 4 V/ns,
functionality is uncertain.
the same amount.
t
and CK# inputs, collectively, during bank active.
can be satisfied prior to the internal PRECHARGE command being issued.
or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either
-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)
minimum.
3.0ns
2.5ns
2.0ns
1.5ns
1.0ns
HP (MIN) is the lesser of
DD
t
DS and
ture and voltage will lie within the outer bounding lines of the V-I curve of
Figure 13 on page 38.
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 13 on page 38.
must not vary more than 4% if CKE is not active while any bank is active.
50/50
2.00
1.60
2.75
2.50
2.10
t
DH for each 100 mV/ns reduction in slew rate. For -5B, -6, and
1.97
1.58
2.71
2.46
2.07
t
QH –
49/51
1.94
1.55
2.68
2.43
2.04
t
t
CL (MIN) and
DQSQ)
37
1.91
1.53
2.64
2.39
2.01
Clock Duty Cycle
48/53
1.88
1.50
2.60
2.35
1.98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – DC and AC
t
1.85
1.48
2.56
2.31
1.95
CH (MIN) actually applied to the device CK
512Mb: x4, x8, x16 DDR SDRAM
47/53
1.82
1.45
2.53
2.28
1.92
1.79
1.43
2.49
2.24
1.89
46/54
©2000 Micron Technology, Inc. All rights reserved.
1.76
1.40
2.45
2.20
1.86
–
300mV or 2.2V (2.4V for
-6T @ t CK = 7.5ns
-75E / -75 @ t CK = 7.5ns
-6 @ t CK = 6ns
-6T @ t CK = 6ns
-5B @ t CK = 5ns
1.73
1.38
2.41
2.16
1.83
45/55
2.13
1.70
1.35
2.38
1.80
t
RAS (MIN)