MT46V64M8P-5B:F Micron Technology Inc, MT46V64M8P-5B:F Datasheet - Page 56

• Manufacturer Part Number: MT46V64M8P-5B:F
• Description: DRAM Chip DDR SDRAM 512M-Bit 64Mx8 2.6V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M8P-5B:F

• Density: 512 Mb
• Maximum Clock Rate: 400 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 64Mx8
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 195mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Burst Length (BL)
Burst Type
Table 34:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Burst Length
2
4
8
Burst Definition
Starting Column Address
A2
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable for both READ and WRITE bursts, as shown in Figure 23 on
page 55. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. BL = 2, BL = 4, or BL = 8 locations
are available for both the sequential and the interleaved burst types. Reserved states
should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block—
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when
BL = 8 (where Ai is the most significant column address bit for a given configuration).
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. For example: for BL = 8, A3–Ai select the eight-data-element block; A0–
A2 select the first access within the block.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 34.
A1
A1
–
–
–
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
56
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
–
–
–
Order of Accesses Within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR SDRAM
Type = Interleaved
©2000 Micron Technology, Inc. All rights reserved.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
–
–
–
Operations