82V2082PF IDT, Integrated Device Technology Inc, 82V2082PF Datasheet - Page 19

• Manufacturer Part Number: 82V2082PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2082PF

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3
3.1
software control mode supports Serial Control Interface, Motorola non-Mul-
tiplexed Control Interface and Intel non-Multiplexed Control Interface. The
Control mode is selected by MODE1 and MODE0 pins as follows:
•
•
•
3.2
the T1E1 bit (GCF, 20H). In E1 application, the T1E1 bit (GCF, 20H) should
be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
by PULSn[3:0] pins on a per channel basis. These pins also determine
transmit pulse template and internal termination impedance. Refer to
HARDWARE CONTROL PIN SUMMARY
3.3
Encoder, an optional Jitter Attenuator, a Waveform Shaper, a set of LBOs,
a Line Driver and a Programmable Transmit Termination.
3.3.1
pin and TDNn pin. In E1 mode, TCLKn is a 2.048 MHz clock. In T1/J1 mode,
TCLKn is a 1.544 MHz clock. If TCLKn is missing for more than 70 MCLK
cycles, an interrupt will be generated if it is not masked.
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SEL bit (TCF0, 04H...). And the active level of the data on TDn/TDPn
and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware
FUNCTIONAL DESCRIPTION
IDT82V2082
The IDT82V2082 can be configured by software or by hardware. The
When the chip is configured by software, T1/E1/J1 mode is selected by
When the chip is configured by hardware, T1/E1/J1 mode is selected
The transmit path of each channel of IDT82V2082 consists of an
The transmit path system interface consists of TCLKn pin, TDn/TDPn
Transmit data is sampled on the TDn/TDPn and TDNn pins by the active
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel non-Multiplexed microcontroller Interface consists of
CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0],
PATTn[1:0], JA[1:0], MONTn, TERMn, EQn, RPDn, MODE[1:0] and
RXTXM[1:0] (n=1, 2). Refer to
MARY
00
01
10
11
FUNCTIONAL DESCRIPTION
CONTROL MODE SELECTION
T1/E1/J1 MODE SELECTION
TRANSMIT PATH
TRANSMIT PATH SYSTEM INTERFACE
for details about hardware control.
Hardware interface
Serial Microcontroller Interface.
Parallel -non-Multiplexed -Motorola Interface
Parallel -non-Multiplexed -Intel Interface
Control Interface Mode
5 HARDWARE CONTROL PIN SUM-
for details.
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
5
19
control mode, the falling edge of TCLKn and the active high of transmit data
are always used.
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to
‘0’. In Dual Rail Mode, both TDPn pin and TDNn pin are used for transmitting
data, the T_MD[1] bit (TCF0, 04H...) should be set to ‘1’.
3.3.2
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on
the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse on
the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are high or low, the TTIPn/TRINGn outputs a space (Refer to
TDNn Pin
path can be selected by setting RXTXM1 and RXTXM0 pins on a global
basis. Refer to
3.3.3
before sending it. The first is to use preset pulse templates for short haul
application, the second is to use LBO (Line Build Out) for long haul appli-
cation and the other way is to use user-programmable arbitrary waveform
template.
the related registers.
PULSn[3:0] pins on a per channel basis. Refer to
PIN SUMMARY
3.3.3.1 Preset Pulse Templates
the G.703 and the measuring diagram is shown in Figure-5. In internal
impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]
bits (TCF1, 05H...) should be set to ‘0000’; if the cable impedance is 120
Ω, the PULS[3:0] bits (TCF1, 05H...) should be set to ‘0001’. In external
impedance matching mode, for both E1/75 Ω and E1/120 Ω cable imped-
ance, PULS[3:0] should be set to ‘0001’.
The IDT82V2082 provides three ways of manipulating the pulse shape
In software control mode, the pulse shape can be selected by setting
In hardware control mode, the pulse shape can be selected by setting
For E1 applications, the pulse shape is shown in
The transmit data from the system side can be provided in two different
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be
In Single Rail mode, when E1 mode is selected, the Encoder can be con-
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
In hardware control mode, the operation mode of receive and transmit
ENCODER
PULSE SHAPER
Description).
for details.
5 HARDWARE CONTROL PIN SUMMARY
5 HARDWARE CONTROL
Figure-4
for details.
May 4, 2009
according to
TDn/TDPn,