82V2082PF IDT, Integrated Device Technology Inc, 82V2082PF Datasheet - Page 47

• Manufacturer Part Number: 82V2082PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2082PF

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

4.3
4.3.1
Table-25 ID: Device Revision Register
Table-26 RST: Reset Register
Table-27 GCF: Global Configuration Register
Table-28 INTCH: Interrupt Channel Indication Register
PROGRAMMING INFORMATION
IDT82V2082
INT_PIN[1:0]
INT_CH[1:0]
INTM_GLB
MONT[1:0]
RST[7:0]
Symbol
Symbol
Symbol
Symbol
ID[7:0]
COPY
T1E1
REGISTER DESCRIPTION
GLOBAL REGISTERS
-
-
(R, Address = 00H)
(W, Address = 01H)
(R/W, Address = 20H)
(R, Address =21H)
7-0
7-0
7-6
1-0
7-2
1-0
Bit
Bit
Bit
Bit
5
4
3
2
Default
Default
Default
Default
000000
00H
00H
00
00
00
0
0
0
1
Current Silicon Chip ID.
Software reset. A write operation on this register will reset all internal registers to their default values, and the status
of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output
are in high impedance state. Note: Bit T1E1 (GCF0) will keep set value and will not be reset.
G.772 monitor
= 00/10: Normal
= 01: Receiver 1 monitors the receive path of channel 2
= 11: Receiver 1 monitors the transmit path of channel 2
Reserved.
This bit selects the E1 or T1/J1 operation mode globally.
= 0: E1 mode is selected.
= 1: T1/J1 mode is selected.
clocking to be settled.
Enable broadcasting mode.
= 0: Broadcasting mode disabled
= 1: Broadcasting mode enabled. Writing operation on one channel's register will be copied exactly to the corre-
sponding registers in other channel.
Global interrupt enable
= 0: Interrupt is globally enabled. But for each individual interrupt, it still can be disabled by its corresponding Inter-
rupt mask Bit.
= 1: All the interrupts are disabled for both channels.
Interrupt pin control
= x0: Open drain, active low (with an external pull-up resistor)
= 01: Push-pull, active low
= 11: Push-pull, active high
Reserved.
INT_CH[n]=0 indicates that an interrupt was generated by channel [n+1].
Note: After bit T1E1 is changed: Before accessing any other regisers a delay of 50us is required to allow the internal
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
47
Description
Description
Description
Description
May 4, 2009