82V2082PF IDT, Integrated Device Technology Inc, 82V2082PF Datasheet - Page 28

• Manufacturer Part Number: 82V2082PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2082PF

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.4.3
intersymbol interference caused by cable attenuation. It can be enabled or
disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
will be set to ‘1’ to indicate the status of equalizer. If EQ_IES bit (INTES,
15H...) is set to ‘1’, any changes of EQ_S bit will generate an interrupt and
EQ_IS bit (INTS0, 18H...) will be set to ‘1’ if it is not masked. If EQ_IES bit
is set to ‘0’, only the ‘0’ to ‘1’ transition of the EQ_S bit will generate an inter-
rupt and EQ_IS bit will be set to ‘1’ if it is not masked. The EQ_IS bit will be
reset after being read.
tude/wave shape of the incoming signals during an observation period. This
observation period can be 32, 64, 128 or 256 symbol periods, as selected
by UPDW[1:0] bits (RCF2, 0BH...). A shorter observation period allows
quicker responses to pulse amplitude variation while a longer observation
period can minimize the possible overshoots. The default observation
period is 128 symbol periods.
adjusted to achieve a normalized signal. LATT[4:0] bits (STAT1, 17H...)
indicate the signal attenuation introduced by the cable in approximately 2
dB per step.
3.4.4
J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for
E1 and -36 dB for T1/J1.
operating mode can be selected by setting EQn on a per channel basis. For
short haul mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
For long haul mode, the receive sensitivity is -43 dB for E1 and -36 dB for
T1/J1. Refer to
3.4.5
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
FUNCTIONAL DESCRIPTION
IDT82V2082
The adaptive equalizer can remove most of the signal distortion due to
When the adaptive equalizer is out of range, EQ_S bit (STAT0, 16H...)
The Amplitude/wave shape detector keeps on measuring the ampli-
Based on the observed peak value for a period, the equalizer will be
For short haul application, the Receive Sensitivity for both E1 and T1/
When the chip is configured by hardware, the short haul or long haul
The Data Slicer is used to generate a standard amplitude mark or a
The CDR is used to recover the clock and data from the received signal.
ADAPTIVE EQUALIZER
RECEIVE SENSITIVITY
DATA SLICER
CDR (Clock & Data Recovery)
5 HARDWARE CONTROL PIN SUMMARY
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
for details.
28
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7
select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to
3.4.8
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
selected. If RCLKE is set to high, the falling edge will be chosen as the active
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR) of the RDPn and RDNn. This is called receiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.4.9
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
ing RPDn pin to high on a per channel basis. Refer to
TROL PIN SUMMARY
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
When the chip is configured by hardware, the operation mode of receive
The receive path system interface consists of RCLKn pin, RDn/RDPn
In hardware control mode, only the active edge of RCLKn can be
The received data can be output to the system side in two different ways:
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
The receive path can be powered down individually by setting R_OFF
In hardware control mode, receiver power down can be selected by pull-
DECODER
RECEIVE PATH SYSTEM INTERFACE
RECEIVE PATH POWER DOWN
5 HARDWARE CONTROL PIN SUMMARY
for more details.
5 HARDWARE CON-
for details.
May 4, 2009