82V2082PF IDT, Integrated Device Technology Inc, 82V2082PF Datasheet - Page 25

• Manufacturer Part Number: 82V2082PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2082PF

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
3.3.4
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100 Ω,
110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
Table-14 Impedance Matching for Transmitter
SCAL[5:0] = 000100 (default), One step change of this value of SCAL[5:0]
results in 25% scaling up/down against the pulse amplitude.
FUNCTIONAL DESCRIPTION
IDT82V2082
The transmit line interface consists of TTIPn and TRINGn pins. The
Note: The precision of the resistors should be better than ± 1%
Sample
10
12
13
14
15
16
11
Cable Configuration
1
2
3
4
5
6
7
8
9
TRANSMIT PATH LINE INTERFACE
T1/133~266 ft
T1/266~399 ft
T1/399~533 ft
T1/533~655 ft
-15.0 dB LBO
-22.5 dB LBO
-7.5 dB LBO
T1/0~133 ft
J1/0~655 ft
E1/120 Ω
0 dB LBO
E1/75 Ω
0000000
0000000
0000000
0000000
0000001
0000011
0001011
0010101
0011001
0100000
0100011
0101010
0000111
0001111
0011100
0100111
UI 1
0101100
0101110
0110000
0110001
0110010
0110010
0110010
0110001
0110000
0101110
0101100
0101001
0100111
0100100
0100010
0100000
UI 2
T_TERM[2:0]
000
001
010
010
011
0010101
0010100
0010001
0010000
0001010
0001001
0011110
0011100
0011010
0011000
0010111
0010011
0001111
0001110
0001101
0001100
UI 3
Internal Termination
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
0001000
0000110
0000101
0000101
0000100
0000100
0000011
0000011
0000010
0000010
0000010
0000001
0000001
0000001
0000001
0000111
PULS[3:0]
UI 4
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
0111
25
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
the cable for one channel.
ance matching for transmitter.
matching for both receiver and transmitter on a per channel basis. If TERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external imped-
ance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
to
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
impedance globally by pulling THZ pin to high. Refer to
TROL PIN SUMMARY
impedance:
•
•
•
•
0 Ω
R
5 HARDWARE CONTROL PIN SUMMARY
Figure-9
In hardware control mode, TERMn pin can be used to select impedance
The TTIPn/TRINGn can also be turned into high impedance globally by
In hardware control mode, TTIPn/TRINGn pins can be turned into high
Besides, in the following cases, TTIPn/TRINGn will also become high
T
Loss of MCLK;
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
shows the appropriate external components to connect with
T_TERM[2:0]
1XX
-
for details.
Table-14
External Termination
is the list of the recommended imped-
PULS[3:0]
0001
0001
for details.
-
5 HARDWARE CON-
May 4, 2009
9.4 Ω
R
-
T