FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 30

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Intel
30
Figure 4. Management Interface Read Frame Structure
Figure 5. Management Interface Write Frame Structure
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
5.2.3.1.2
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in
MDIO Interface timing is given in
MDIO
(Read)
(Write)
MDC
MDIO
MDC
High Z
Idle
Preamble
Figure 4
32 "1"s
Preamble
32 "1"s
MDIO Frame Structure
0
0
ST
and
ST
1
1
Figure 5
1
0
Op Code
Op Code
1
0
(Read and Write).
Write
A4
A4
Chapter 7.0, “Electrical Specifications”.
PHY Address
PHY Address
A3
A3
A0
A0
Write
R4
R4
Register Address
Register Address
R3
R3
R0
R0
1
Z
Around
Around
Turn
Turn
0
0
D15
D15
D15
D14
D14
Document Number: 249414-003
Data
Read
D14
Data
Revision Date: June 18, 2004
D1
D1
D1
D0
D0
Datasheet
Idle
B3490-01
Idle
B3489-01