FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 61

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

5.10.4
5.10.5
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Table 16. BSR Mode of Operation
Table 17. Device ID Register for Intel
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage.
Device ID Register
Table 17
characters, see the specification update for the LXT971A Transceiver.
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE
Mode
Bits 31:28
Version
(1111 1110), which becomes 111 1110.
1
2
3
4
XXXX
lists the bits for the Device ID register. For the current version of the JEDEC continuation
Part ID (Hex)
System Function
Bits 27:12
Description
03CB
Capture
Update
Shift
Intel
®
LXT971A Transceiver
JEDEC Continuation Characters
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 16
Bits 11:8
0000
lists the four BSR modes of operation.
JEDEC ID
111 1110
Bits 7:1
1
Reserved
Bit 0
1
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