FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 97

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Table 55. Configuration Register - Address 16, Hex 10
Table 55
16.4:3
1. R/W = Read /Write
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.2
16.1
16.0
Bit
lists configuration bits.
Reserved
Force Link Pass
Transmit Disable
Bypass Scrambler
(100BASE-TX)
Reserved
Jabber
(10BASE-T)
SQE
(10BASE-T)
TP Loopback
(10BASE-T)
CRS Select
(10BASE-T)
Sleep Mode
PRE_EN
Sleep Timer
Fault Code
Alternate NP
feature
Fiber Select
Enable
Name
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Force Link pass
0 = Normal operation
1 = Disable Twisted Pair transmitter
0 = Normal operation
1 = Bypass Scrambler and Descrambler
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Disable Jabber Correction
0 = Disable Heart Beat
1 = Enable Heart Beat
0 = Normal operation
1 = Disable TP loopback during half-duplex
0 = Normal Operation
1 = CRS deassert extends to RX_DV deassert
0 = Disable Sleep Mode
1 = Enable Sleep Mode
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
NOTE: Preamble is always enabled in 100 Mbps
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
0 = Disable FEFI transmission
1 = Enable FEFI transmission
0 = Disable alternate auto negotiate next page
1 = Enable alternate auto negotiate next page
This bit enables or disables the register bit 6.5
capability.
0 = Select TP mode.
1 = Select fiber mode.
Intel
operation
CRS is asserted.
feature.
feature.
®
operation.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
determined
Default
value is
determined
by state of
pin 26/G2
(SD/TP_L).
SLEEP pin
by state of
Default
value is
Default
32/H7.
00
0
0
0
0
0
0
0
0
1
0
1
0
97