FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet
FLLXT1000BA.C4QE000
Specifications of FLLXT1000BA.C4QE000
Related parts for FLLXT1000BA.C4QE000
FLLXT1000BA.C4QE000 Summary of contents
Page 1
... The LXT1000 transceiver supports Gigabit Ethernet over copper twisted-pair connections and supplies all of the physical layer (PHY) functions needed to interface a Gigabit Ethernet controller to a 100-meter CAT5 twisted-pair connection. The device incorporates Intel’s high- efficiency Optimal Signal Processing (OSP digital and analog signal processing to produce a truly optimal device. ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
Page 3
... TBI Configuration (1000BASE-T Only)...................................................28 2.3.4 TBI Communication Between MAC and PHY ........................................29 2.3.4.1 Transmit Mode – Data Traffic from MAC to PHY ......................30 2.3.4.2 Receive Mode – Data Traffic from PHY to MAC .......................31 2.3.5 MAC Data Interface Control ...................................................................31 2.3.6 MDIO/MDC Management Interface........................................................31 2.3.6.1 Interrupts ...................................................................................32 2 ...
Page 4
Contents 2.4.6.1 False Link .................................................................................. 40 2.4.6.2 Auto-Negotiation........................................................................ 40 2.4.6.3 Parallel Detection ...................................................................... 41 2.4.6.4 Forced Operation ...................................................................... 42 2.4.7 Establishing and Maintaining the Link .................................................... 42 2.4.7.1 1000BASE-T ............................................................................. 42 2.4.7.2 100BASE-TX ............................................................................. 42 2.4.7.3 10BASE-T ................................................................................. 43 2.4.8 ...
Page 5
Mbps Operation..............................................................................................62 2.7.1 Transmitting/Receiving...........................................................................63 2.7.2 Polarity Correction..................................................................................63 2.7.3 Link Test.................................................................................................63 2.7.4 Link Failure.............................................................................................63 2.7.5 SQE (Heartbeat).....................................................................................63 2.7.6 Jabber ....................................................................................................64 2.7.7 Preamble Generation Mode ...................................................................64 2.8 LXT1000 Operating Requirements......................................................................64 2.8.1 Power .....................................................................................................64 2.8.2 Clock ......................................................................................................64 2.8.3 RBIAS.....................................................................................................64 2.8.4 GBIAS ...
Page 6
... MDIO Read Frame Format ................................................................................. 32 12 MDIO Write Frame Format.................................................................................. 32 13 Interrupt Handling................................................................................................ 33 14 Quick Status Register ......................................................................................... 35 15 PHY Address Determination via LED balls ......................................................... 36 16 Overview of Link Establishment .......................................................................... 40 17 Link Speed and Corresponding Clock Frequency Changes ............................... 46 18 1000BASE-T Functions Overview....................................................................... 47 19 1000BASE-T Transmit Flow and Line Coding Scheme ...................................... 49 20 1000BASE-T Receive Flow ...
Page 7
... MAC Interface Transmit Signal Mapping.............................................................26 13 MAC Interface Receive Signal Mapping..............................................................26 14 Test Loopback Operation ....................................................................................28 15 Configuring the LXT1000 via Hardware Control Interface...................................34 16 LED Status Indication / PHY Addressing ............................................................36 17 Boundary Scan Supported Instructions...............................................................37 18 BSR Mode of Operation ......................................................................................37 19 JTAG ID Register ................................................................................................38 20 Initialization Modes ...
Page 8
... Register Set ........................................................................................................ 90 54 Control Register (Address 0)............................................................................... 91 55 Status Register (Address 1) ................................................................................ 92 56 PHY Identification Register 1 (Address 2)........................................................... 92 57 PHY Identification Register 2 (Address 3)........................................................... 93 58 Auto-Negotiation Advertisement Register (Address 4)1 ..................................... 93 59 Auto-Negotiation Link-Partner Base Page Ability Register (Address 5).............. 94 60 Auto-Negotiation Expansion Register (Address 6).............................................. 95 61 Auto-Negotiation Next Page Transmit Register (Address 7)............................... 96 62 Auto-Negotiation Link Partner Received Next Page Ability Register (Address 8) ...
Page 9
Revision History Revision Date 002 July 2001 Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 Page # Description 28 Add “Test Loopback” to the Functional Description section. Add footnote to Table 27 in the Applications Information section referring ...
Page 10
...
Page 11
Figure 1. LXT1000 Block Diagram 4DPAM5 EnDec, Scrambler, Viterbi, & DFE Controller MAC Interface GMII MII 100BASE-Tx Serial 4B/5B EnDec 10BASE-T Manchester EnDec MDDIS MDIO & MDIO Management / MDIO Register MDC Mode Select Set Logic MDINT Datasheet Document #: ...
Page 12
LXT1000 — Gigabit Ethernet Transceiver 1.0 Ball Assignments and Signal Descriptions Figure 2. LXT1000 PBGA Assignments gnd gnd gnd gnd gnd gnd gnd gnd B gnd gnd gnd gnd gnd gnd ...
Page 13
Table 1. Signal Type Abbreviations Symbol Signal Type I Input Standard input-only signal. Input LHR Latched on Low-to-High edge of RESET; ignored thereafter. Latched, L-H Reset Input, Latched on Low-to-High edge of RESET; used thereafter only if Manual Control mode ...
Page 14
LXT1000 — Gigabit Ethernet Transceiver Table 2. LXT1000 GMII Signal Descriptions (Continued) 1 Ball # Symbol Type B11 RXD7 C10 RXD6 B9 RXD5 E10 RXD4 O C8 RXD3 E8 RXD2 D7 RXD1 E6 RXD0 C12 RX_DV O E13 RX_ER O ...
Page 15
... GMII Control Interface Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 2.5 MHz. Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and the management function. 1 Description Twisted-Pair Positive and Negative. For 1000BASE-T operation, all four pair are both input and output at the same time ...
Page 16
LXT1000 — Gigabit Ethernet Transceiver Table 4. LXT1000 Configuration Signal Descriptions (Continued) Ball # Symbol Type I, MD DUPLEX/ Y22 TX_TCLKN O L2 AN_RSTRT I, MD R23 SMART_SPD LHR I, MD PAUSE/ AA22 TX_TCLKP O B21 MASTER I, MD T22 ...
Page 17
... After reset, this ball is an LED output indicating link establishment at any speed. The LXT1000 automatically determines whether this output is active High or active Low. MDIO Address 0. During power-up or reset, this ball is read to determine bit 0 of the LXT1000’s MDIO Address. “PHY Address “PHY Address 17 ...
Page 18
LXT1000 — Gigabit Ethernet Transceiver Table 6. LXT1000 Miscellaneous Signal Descriptions Ball # Symbol C22 QSTAT O, PU D19 QCLK I L5 MDDIS I K3 MDINT O AC23 XI I AA24 AB14 RBIAS AI D9, D11, D12, E12, ...
Page 19
Table 7. LXT1000 Boundary Scan Signal Descriptions Ball # Name I/O N5 TCK I N3 TDI I P4 TDO O M4 TMS I P2 TRST I 1. I/O Column Coding Input Output Table 8. LXT1000 Power ...
Page 20
... Network Interface The LXT1000 uses a single, common network interface to support 1000BASE-T, 100BASE-TX, and 10BASE-T. This physical interface consists of four signal pairs that are used for 1000 Mbps transmission. (Only two pairs are needed for 10/100 Mbps.) Each signal pair consists of two bidirectional balls that transmit and receive at the same time ...
Page 21
... Hardware Control Interface The LXT1000 is configurable at power up or hardware reset. Configuration options and operational settings of the device include such variables as link establishment, MAC interface operation and control, and physical address of the device. See page 33. 2.1.5 JTAG Boundary Scan Interface The LXT1000 includes an IEEE JTAG1149.1 boundary scan test port for board level testing. ...
Page 22
LXT1000 — Gigabit Ethernet Transceiver Figure 3. LXT1000 Applications NIC Switch 22 PC Bus MAC LXT1000 Data Bus LXT1000 LXT1000 MAC LXT1000 LXT1000 Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 ...
Page 23
XI OSCILLATOR GTX_CLK TX_CLK SERIALIZER TXD[7:0] TX_EN 4B5B TX_ER CONTROLLER ENCODER CRS INTERFACE ( MII / GMII ) COL RX_CLK RXD[7:0] RX_DV SIDE STREAM RX_ER SCRAMBLER MDC SERIAL MDIO PORT AN_EN SPEED[1:0] QSTAT PAUSE DUPLEX RPTR CONFIG MDDIS CROSS AN_RSTRT ...
Page 24
... The network physical interface consists of passive devices and magnetics. For 1000BASE-T, all four pairs are used in both directions at the same time. For 10/100 links and during auto-negotiation, only pairs A and B are used ...
Page 25
Table 10. Crossover Control and Automatic Detection Crossover Input CROSS = Low CROSS = High CROSS = Open 2.3.2 MAC Data Interface The MAC Data Interface has two basic configurations as selected by the TBI configuration pin: • GMII - ...
Page 26
LXT1000 — Gigabit Ethernet Transceiver Table 12. MAC Interface Transmit Signal Mapping MAC Interface 1000BASE-T Ball # GMII Mode (8B) D17 25 MHz ref. B17 GTX_CLK C18 TX_ER E18 C20 TXD<7> E20 TXD<6> D21 TXD<5> G22 TXD<4> F23 H23 J22 ...
Page 27
GMII Mode (1000 BASE-T) In GMII Mode, the LXT1000 supplies the following: • RX_CLK (125 MHz) • Eight receive data bits • Carrier sense • Collision detect • Receive error signal The MAC supplies a 125 MHz GTX clock, ...
Page 28
LXT1000 — Gigabit Ethernet Transceiver The relationship between 10 Mbps Serial Interface and the 10 Mbps MII Interface is shown in Figure 8. Figure 7. Serial Interface LXT1000 RX_CLK Figure 8. Relationship between 10 Mbps Serial Interface and 10 Mbps ...
Page 29
... PHY to the MAC. (See IEEE 802.3z Clause 36.2.4.15.1 for more information.) This action results in the addition of a one-byte carrier extend, which the MAC may interpret as an error in approximately half of the transmitted frames ...
Page 30
... Frames Ending on an Even Byte The PHY interprets the frames correctly but must realign itself so that they end on an even code group. When the PHY resets or realigns, it changes the even and odd byte designations. The data are then serialized and passed onto the twisted-pair for transmission ...
Page 31
... MDIO line for the entire frame. For a read operation, a turn-around time is inserted in the frame to allow the PHY to drive data back to the MAC. The LXT1000 supports a maximum frequency on MDC of 2.5 MHz. The MDIO frame structure starts with a 32-bit preamble, which is required by the LXT1000. It includes a start-of-frame marker, an op-code, a 10-bit address field, and a 16-bit data field ...
Page 32
... Polarity • Smartspeed Select • Error Counters Full • Auto-negotiation Turn PHY Address Register Address Around Write PHY Address Register Address Write D1 D15 D15 D14 D14 Data Idle Read D15 D14 Turn Data Idle Around Figure 13. The Interrupt Datasheet Document #: 249276 Revision #: 002 Rev ...
Page 33
... Hardware Control Interface Configuration options and operational settings of the device include such variables as link establishment, MAC interface operation and control, and physical address of the device. Individual chip addressing allows multiple LXT1000 devices to share the GMII in either mode. all hardware selectable configurations. Some configuration bits are read only at hardware reset. ...
Page 34
... Quick Status data ball (QSTAT). Utilizing this single ball allows the MAC to be constantly aware of what operations the PHY is performing. A separate, 25 MHz clock input line (QCLK) provides synchronization for the data ball. Thus, an ASIC can monitor multiple PHY devices using a single clock ...
Page 35
... LXT1000 sources this status information on the falling edge of QCLK. This information provides a continuous status update of several different attributes and modes of the PHY, and can be used to sense RX, TX, and COL as well as to monitor the status and speed of the auto-negotiation process. The information is provided on an unsolicited basis, without having to issue read requests, which is ideal for hardware applications that require constant monitoring of link status with minimal interaction ...
Page 36
... LED ball and ground. The polarity of the LEDs is automatically detected and corrected. If LEDs are not required for the application, only a resistor is required to set the PHY address. The LED balls are designed to drive 10 mA. They will be open drain/source depending on the external circuit configuration ...
Page 37
... The LXT1000 includes an IEEE JTAG1149.1 boundary scan test port for board level testing. All digital I/O balls are accessible. The physical interface consists of five balls (TRST, TMS, TDI, TDO, and TCK), and includes a state machine, data register array, and instruction register. Pull each of these balls High except TRST, which is pulled Low ...
Page 38
... Version Part ID xxxx 3E8 1. The JEDEC 8-bit identifier. And the MSB is for parity and is ignored. Intel’s JEDEC (1111 1110) which becomes 111 1110. 2.4 Initialization 2.4.1 Power-Up At power-up, the LXT1000 initializes all internal PLLs and analog functions and reads its hardware configuration balls ...
Page 39
Table 20. Initialization Modes Initializes PLL and Mode Analog Functions Power-Up H/W Reset H/W Power-Down Recovery S/W Power-Down Recovery S/W Reset 2.4.6 Determining Link State The LXT1000 and its link partner determine the type of link established through one of ...
Page 40
LXT1000 — Gigabit Ethernet Transceiver Figure 16. Overview of Link Establishment Forced Operation 0 Speed? 0.13 10M Send NLP N Y Detect 10 Mbps ? Taking Down Bringing Up Link Link Bit 0.8 sets Duplex 2.4.6.1 False Link The LXT1000 ...
Page 41
Link information is exchanged in 16-bit words called “Pages”. 10/100 auto-negotiation requires only one page, which is called the “Base Page” and is exchanged through Registers 4 and 5. 1000 auto-negotiation requires four pages: a base page and three next ...
Page 42
LXT1000 — Gigabit Ethernet Transceiver 2.4.6.4 Forced Operation Forced operation can be used to establish 10 and 100 links, and 1000 links for test purposes. In this method, auto-negotiation is disabled completely, and the link state of the LXT1000 is ...
Page 43
... Flow Control 2.4.9.1 SmartSpeed SmartSpeed is an enhancement to auto-negotiation that allows the LXT1000 to react intelligently to network conditions that prohibit establishment of a 1000BASE-T link, such as cable problems. Such problems may allow auto-negotiation to complete, but then inhibit completion of the training phase. Normally 1000BASE-T link fails, the LXT1000 returns to the auto-negotiation state with the same speed settings indefinitely ...
Page 44
LXT1000 — Gigabit Ethernet Transceiver 2.4.9.1.1 Using SmartSpeed Smartspeed is enabled by pulling SMART_SPD High or by setting 16 When SmartSpeed downgrades the LXT1000 advertised capabilities, it sets bit 18.9. When link is established, its speed is indicated ...
Page 45
Table 23. Pause and Asymmetric Pause Settings Pause ASM_DIR settings Local Setting - (4.11) and Remote (5.10) Local (4.10 Both ASM_DIR = Either or both ASM_DIR = 0 Either or both = 0 2.4.10 ...
Page 46
LXT1000 — Gigabit Ethernet Transceiver 2. The crystal clock (XI) and the GTX_CLK are continuous. Both are input signals. Figure 17. Link Speed and Corresponding Clock Frequency Changes Link Up Gigabit 25 MHz TX_CLK 125 MHz RX_CLK 100BASE-T 25 MHz ...
Page 47
Figure 18. 1000BASE-T Functions Overview GMII Mode DSP ECHO, NEXT, FEXT Cancellers AGC, A/D, Timing Recovery Hybrid 2.5.2 Transmit Functions This section describes functions used when the Media Access Controller (MAC) transmits data through the LXT1000 and out onto the ...
Page 48
LXT1000 — Gigabit Ethernet Transceiver 2.5.2.1 8B/10B Decoder The 8B/10B is used only when the MAC interface is configured for TBI mode. In that case, it converts 10B codes transmitted by the MAC into 8B (GMII) data. Note that only ...
Page 49
... Figure 19. 1000BASE-T Transmit Flow and Line Coding Scheme GMII Scrambler 2.5.2.10.1 Scrambler Polynomials (Master PHY Mode (Slave PHY Mode) Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 Gigabit Ethernet Transceiver — LXT1000 4D 8 Trellis 9 PAM-5 Encoder PAM-5 Encoded Output to 4-Pair UTP Line 49 ...
Page 50
LXT1000 — Gigabit Ethernet Transceiver Figure 20. 1000BASE-T Receive Flow Polynomial D3 8 bits Descrambler GMII 2.5.3 Receive Functions This section describes functions which are used when the LXT1000 receives data from the ...
Page 51
Far-end crosstalk (FEXT) • Propagation delay variations between channels 120 ns. • Extraneous tones that have been coupled into the receive path. The adaptive filter coefficients are initially set during the training phase. They are continuously ...
Page 52
... Packet concatentation, which allows MACs in half-duplex applications to concatenate packet maximum length of 8 KB. Gaps between packets are filled using a special symbol allowing the PHY to maintain ownership of the link. • Jumbo frames. For full-duplex operations, the LXT1000 allows jumbo frames KB, with up to +/- 200 ppm of frequency tolerance on any clock. ...
Page 53
Figure 22. 1000BASE-T Transmission (No Errors, No Collision, No Carrier Extension) GTX_CLK (input) TX_EN (input) CRS (output) PREAMBLE/SFD TXD<7:0> (input) TP<A:D> (output) IDLE SSD Figure 23. 1000BASE-T Reception (No Errors, No Collision, No Carrier Extension) IDLE SSD TP<A:D> ...
Page 54
LXT1000 — Gigabit Ethernet Transceiver 2.5.4.1.3 False Carrier Detection If the LXT1000 receives a false carrier, defined as a packet that does not have an SSD, it responds by asserting RX_ER and driving an “0E” on the RX_D lines. Figure ...
Page 55
Figure 27. 1000BASE-T Reception with Error IDLE SSD TP<A:D> (input) RXD<7:0> (output) PREAMBLE/SFD CRS (output) RXDV (output) RXER (output) 2.5.4.1.5 Carrier Extend/Packet Concatenation To extend carrier at the end of a packet, the MAC asserts TX_ER as it ...
Page 56
LXT1000 — Gigabit Ethernet Transceiver Figure 28. 1000BASE-T Transmission, Carrier Extend and Packet Concatenation GTX_CLK (input) TX_EN (input) TX_ER (input) CRS (output) PACKET TXD<7:0> (input) TP<A:D> (output) IDLE Packet Figure 29. 1000BASE-T Reception, Carrier Extension and Packet Concatenation IDLE Packet ...
Page 57
Figure 30. 1000BASE-T Transmission Extend - Packet Concatenation and Carrier Extension, with Errors GTX_CLK (input) TX_EN (input) TX_ER (input) CRS (output) PACKET TXD<7:0> (input) TP<A:D> (output) IDLE Packet Figure 31. 1000BASE-T Reception Extend - Packet Concatenation and Carrier Extension, with ...
Page 58
LXT1000 — Gigabit Ethernet Transceiver Figure 32. Protocol Sublayers and Associated Functions PCS Sublayer PMA Sublayer PMD Sublayer 2.6.2 Digital Functions 2.6.2.1 4B/5B Encoder The 4B/5B encoder translates 4B data nibbles to one symbols. Of the 32 ...
Page 59
MLT3 Encoder The MLT3 encoder translates the encoded, scrambled data into an MLT3 waveform, which uses three signal levels (+1, 0, -1) that follow each other in an infinitely repeating loop (+1 -> 0 -> -1 -> 0 -> ...
Page 60
LXT1000 — Gigabit Ethernet Transceiver 2.6.3.2 Collision Detection If the LXT1000 is in half-duplex, and it sends and receives a packet at the same time, it asserts its collisions (COL) output (see 2.6.3.3 False Carrier Detection If the LXT1000 detects ...
Page 61
Table 24. 4B/5B Coding (Continued) 4B Code Code Type DATA ...
Page 62
LXT1000 — Gigabit Ethernet Transceiver Figure 35. 100BASE-T Transmission (No Errors, No Collision, No Carrier Extension) TX_CLK TX_EN TXD<3:0> CRS COL Figure 36. 100BASE-T Reception (No Errors, No Collision, No Carrier Extension) RX_CLK RX_DV RXD<3:0> SFD ...
Page 63
Transmitting/Receiving In 10 Mbps mode, when the receiver detects preamble, it always asserts CRS immediately. Its next action depends on the state of bit 16. the LXT1000 strips the entire 10 Mbps preamble, asserting RX_DV ...
Page 64
LXT1000 — Gigabit Ethernet Transceiver 2.7.6 Jabber If MAC transmission exceeds the jabber timer, the LXT1000 will disable the transmit and loopback functions and assert the COL ball. The LXT1000 automatically exits jabber mode 250- 750 ms after the MAC ...
Page 65
GBIAS Tie the GBIAS balls together, then tie to the anode of a 0.1 f capacitor, and the cathode of this capacitor to ground. Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 Gigabit Ethernet Transceiver — LXT1000 ...
Page 66
LXT1000 — Gigabit Ethernet Transceiver 3.0 Application Information 3.1 Design Recommendations 3.1.1 Device Placement The LXT1000 should be placed as close to the magnetics and RJ-45 connector as is possible, and no more than inches away from ...
Page 67
Decoupling Capacitors A decoupling capacitor must be placed near each LXT1000 VCC ball. A 0.01 F value is recommended. Liberal and extensive use of decoupling capacitors throughout the design is highly recommended. The self-resonant frequency of the decoupling capacitors ...
Page 68
LXT1000 — Gigabit Ethernet Transceiver 3.1.8 Master/Slave Relationship Details Resolution of the Master-Slave relationship is a key part of gigabit auto-negotiation. As shown in Figure 38, every Gigabit link has a “Master” side and a “Slave” side. The Master synchronizes ...
Page 69
If bit 9. this node must be the master. If bit 9. this node must be the slave. Bit 9.11 the default state. By default, bit 9.11 is not used. Bit 9.10 Bit 9.10 ...
Page 70
... Disabling the encoder causes the MII interface to operate as a 5-bit symbol mode interface, rather than the normal 4-bit mode transmission. RXD4 and TXD4 accommodate MACs accepting 5-bit symbols. In this “5B” mode, the MAC is responsible for generating all PHY layer encoding, including SFD, EFD, and idle code. ...
Page 71
Magnetics Information The LXT1000 features a simple 1:1 turns ratio requirement for connection to the transmission line. The hybrid is integrated into the LXT1000 and is not required in the magnetic. Refer to for transformer requirements. Transformers meeting these ...
Page 72
... TX_CLK MAC / GMAC GTX_CLK RX_CLK RX_DV RX_ER RXD<7:0> CRS COL 72 groups similar signals; it does not portray the actual chip pin out. The MII is details the twisted-pair interface of a typical NIC application. LXT1000 (10/100/1000BASE-TPHY RJ- Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 ...
Page 73
Figure 40. Typical Configuration - GMII Interface GND TX_CLK GTX_CLK TXD<7:0> TX_EN GMII TX_ER Data CRS I/F COL RX_DV RXD<7:0> RX_CLK RX_ER GMII MDC Management MDIO AN_EN SPEED<2:0> DUPLEX SMART_SPD MASTER Configuration PAUSE Control ANISOL I/F SER10 CROSS TBI MDDIS ...
Page 74
LXT1000 — Gigabit Ethernet Transceiver Figure 41. NIC Application - Twisted-Pair Interface LXT1000 74 TPOPA 100 3.3VCCA 0.01 F TPONA TPOPB 100 3.3VCCA 0.01 F TPONB TPOPC 100 3.3VCCA 0.01 F TPONC TPOPD 100 3.3VCCA 0.01 F TPOND NOTE: Refer ...
Page 75
Test Specifications Note: Table 29 through Table 52 the LXT1000 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in operating conditions specified in (Test Specifications remain under development.) Table 29. Absolute ...
Page 76
LXT1000 — Gigabit Ethernet Transceiver Table 32. GMII General AC Specifications Parameter Symbol Clock Rise Time tR Clock Fall Time tF Clock Slew Rate Input Low Voltage AC Vil_ac Input High Voltage AC Vih_ac GTX_CLK Frequency GTX_CLK, RX_CLK Time High ...
Page 77
Table 34. Required Clock Characteristics Parameter Frequency Frequency Stability Effective Series Resistance Rise Time Jitter Table 35. 1000BASE-T Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal scaling Output Droop Transmitter Distortion Peak-to-Peak Transmitter Timing Jitter Measurements Ref. ...
Page 78
LXT1000 — Gigabit Ethernet Transceiver Table 37. 10BASE-T Transceiver Characteristics Parameter Transmitter Peak differential output voltage Transition timing jitter added by the MAU and PLS sections Receiver Receive Input Impedance Differential Squelch Threshold 1. Typical values are at 25 °C ...
Page 79
Table 39. 1000BASE-T GMII Transmit Timing Parameters Parameter TXD<7:0>, TX_EN, TX_ER Setup to GTX_CLK High TXD<7:0>, TX_EN, TX_ER Hold from GTX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to twisted-pair out (Transmit latency) 1. ...
Page 80
LXT1000 — Gigabit Ethernet Transceiver 4.2 100BASE-TX Timing Parameters Figure 44. 100BASE-TX Transmit Timing TXCLK TX_EN TXD<3:0> TPOP CRS Table 41. GMII - 100BASE-TX Transmit Timing Parameters / 4B Mode Parameter TXD<3:0>, TX_EN, TX_ER Setup to TX_CLK High TXD<3:0>, TX_EN, ...
Page 81
Figure 45. 100BASE-TX Receive Timing TPIP CRS RX_DV RXD<3:0> RX_CLK COL Table 42. GMII - 100BASE-TX Receive Timing Parameters / 4B Mode Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High Receive start of ...
Page 82
LXT1000 — Gigabit Ethernet Transceiver 4.3 10BASE-T Timing Parameters Figure 46. 10BASE-T MII Transmit Timing t1 TX _CLK CRS TPO Table 43. GMII - 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, ...
Page 83
Figure 47. 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RXER CRS TPI COL Table 44. GMII - 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPI in to RXD out ...
Page 84
LXT1000 — Gigabit Ethernet Transceiver Table 45. 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not ...
Page 85
Figure 50. 10BASE-T Serial Transmit Timing TX_EN t1 TX_CLK TXD TPO Table 47. 10BASE-T Serial Transmit Timing Parameter TX_EN setup from TX_CLK TXD<0> setup from TX_CLK TX_EN hold after TX_CLK TXD<0> hold after TX_CLK Transmit Start-up delay Transmit Latency 1. ...
Page 86
LXT1000 — Gigabit Ethernet Transceiver Table 48. 10BASE-T Serial Start-of-Frame Timing Parameter Decoder Acquisition Time CRS turn-on delay RXD setup from RX_CLK RXD hold from RX_CLK 1. Typical values are at 25 °C and are for design aid only; not ...
Page 87
Auto-Negotiation Timing Parameters Figure 53. Fast Link Pulse Timing Clock Pulse TPOP t1 Figure 54. FLP Burst Timing FLP Burst TPOP t4 Table 50. Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock ...
Page 88
... Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing (Min) (Min 300 ns 1 Sym Min Typ Max 300 Units Test Conditions ns When sourced by STA ns When sourced by STA ns When sourced by PHY Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 ...
Page 89
QSTAT Timing Parameters Figure 57. QSTAT Write Timing QCLK QSTAT Table 52. QSTAT Timing Parameters Parameter QCLK to QSTAT Output delay QCLK Frequency QCLK Duty Cycle 1. Typical values are at 25° C and are for design aid only; ...
Page 90
... Table 53 • Base registers (0 through 10 and 15) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signalling for 10/100/ 1000 Mbps Auto-Negotiation” sections of the IEEE 802.3. • Additional registers (16 through 22) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions ...
Page 91
... Enable Auto-Negotiation Process Auto-Negotiation 0. Disable Auto-Negotiation Process Enable This bit must be enabled for 1000BASE-T operation Power down 0.11 Power Down 0 = Normal operation 1 = Electrically isolate PHY from GMII 0.10 Isolate 0 = Normal operation Restart 1 = Restart Auto-Negotiation Process 0 Normal operation Auto-Negotiation 1 = Full Duplex 0.8 ...
Page 92
... PHY able to operate at 10 Mbps in full-duplex mode 1.12 Full Duplex 0 = PHY not able to operate at 10 Mbps full-duplex mode 10 Mbps 1 = PHY able to operate at 10 Mbps in half-duplex mode 1.11 Half Duplex 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to perform full-duplex 100BASE-T2 100BASE-T2 1 ...
Page 93
... Figure 58. PHY Identifier Bit Mapping Organizationally Unique Identifier PHY ID Register #1 (address 2) = 0013 The Intel OUI is 00207B hex Table 58. Auto-Negotiation Advertisement Register (Address 4) Bit Name 1 = Manual Control of Next Page (Software) 4.15 Next Page 0 = Device Control of Next Page (Auto) 4.14 Reserved 1 = Remote fault. ...
Page 94
LXT1000 — Gigabit Ethernet Transceiver Table 58. Auto-Negotiation Advertisement Register (Address 4) Bit Name 4.12 Reserved Advertise Asymmetric Pause direction bit. This bit is used in 4.11 ASM_DIR conjunction with PAUSE. Advertise to Partner that Pause operation as defined in ...
Page 95
Table 59. Auto-Negotiation Link-Partner Base Page Ability Register (Address 5) Bit Name Advertise Asymmetric Pause direction bit. This bit is used in conjunction with PAUSE. 5.11 LP ASM_DIR 1 = Link Partner is capable of asymmetric pause Link ...
Page 96
LXT1000 — Gigabit Ethernet Transceiver Table 60. Auto-Negotiation Expansion Register (Address 6) Bit Name 1 = Local device is next page able 6.2 Next Page Able 0 = Local device is not next page able Indicates that a new page ...
Page 97
... Disable MASTER-SLAVE Manual configuration value 1 = Configure PHY as MASTER during MASTER-SLAVE Master/Slave negotiation, only when 9.12 is set to logical one. 9.11 Config Value 0 = Configure PHY as SLAVE during MASTER-SLAVE negotiation, only when 9.12 is set to logical one Multi-port Device (MASTER) 9.10 Port Type 0 = Single-port (SLAVE) This bit is only used when 9 ...
Page 98
... Half Duplex 0 = PHY able to perform half-duplex 1000BASE PHY able to perform full-duplex 1000BASE-T 1000BASE-T 15.13 Full Duplex 0 = PHY not able to perform full-duplex 1000BASE PHY able to perform half-duplex 1000BASE-T 1000BASE-T 15.12 Full Duplex 0 = PHY able to perform half-duplex 1000BASE-T 15.11:0 Reserved Ignore when read 1 ...
Page 99
Table 66. Port Configuration Register (Address 16) Bit Name 16.15 Reserved Always set to 0. 16.14 Reserved Always set Disable twisted-pair transmitter 16.13 Transmit Disable 0 = Normal Operation Bypass Scrambler 1 = Bypass Scrambler and ...
Page 100
LXT1000 — Gigabit Ethernet Transceiver Table 67. Quick Status Register (Address 17) Bit Name 17.15 0 17.15:14 Data Rate LXT1000 is transmitting a packet 17.13 Transmit Status 0 = LXT1000 is not transmitting a packet ...
Page 101
Table 68. Interrupt Enable Register (Address 18) Bit Name 18.15:14 Reserved Write as 0; ignore on read. Mask for auto-negotiation fault. 18:13 AN_FAULT 1 = Enable event to cause interrupt not allow event to cause interrupt 18.12 ...
Page 102
LXT1000 — Gigabit Ethernet Transceiver Table 69. Interrupt Status Register (Address 19) Bit Name 19.15:14 Reserved Ignore Auto-negotiation Fault Event occurred. 19.13 AN_FAULT 1 = Indicates fault detected 0 = Indicates no an_fault occurred. 19.12 Reserved - Crossover Event Status ...
Page 103
Table 70. LED Configuration Register (Address 20) Bit Name 00 = Collision indication LEDC 01 = Blink 20.15:14 Programming bit Off 00 = Receive indication 01 = Blink LEDR 20.13:12 Programming bit ...
Page 104
LXT1000 — Gigabit Ethernet Transceiver Table 71. Port Control Register (Address 21) Bit Name Enables TX_TCLK outputs for jitter testing. The output signal appears at the PAUSE/TX_TCLKP and DUPLEX/TX__TCLKN 21.15 TX_TCLK balls. Note: Must be measured with a differential probe. ...
Page 105
Mechanical Specification Figure 59. Preliminary PBGA Package Specification Datasheet Document #: 249276 Revision #: 002 Rev. Date: 07/20/01 Gigabit Ethernet Transceiver — LXT1000 105 ...
Page 106
... Product Revision xn Temperature Range Internal Package Designator xxxx IXA Product Prefix LXT IXE IXF IXP Intel Package Designator Tray MM Tape & Reel MM 837274 — = Tray = Tape and reel = Pre-production material = Production material = 2 Alphanumeric characters = Ambient (0 - 55° Commercial (0 - 70° Extended (-40 - +85° C) ...