FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 67

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

3.1.3.1
3.1.4
3.1.5
3.1.6
3.1.7
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
Decoupling Capacitors
A decoupling capacitor must be placed near each LXT1000 VCC ball. A 0.01 F value is
recommended. Liberal and extensive use of decoupling capacitors throughout the design is highly
recommended. The self-resonant frequency of the decoupling capacitors should be at least 125
MHz.
RBIAS and GBIAS Requirements
For RBIAS and GBIAS requirements, see
Twisted-Pair Layout
Each of the four signal pairs should be laid out differentially. The two traces must be kept close
together, with no intervening traces or components other than the passive termination network.
Layer changes should be avoided if at all possible. Keep traces short as possible, and shielded
above and below with a quiet ground plane if possible.
The device-side center-tap of each winding must be supplied with the same 3.3V used to supply the
analog VCC balls of the LXT1000. Each center-tap should be supplied with its own 0.01 f
decoupling capacitor to circuit ground.
Transformer isolation voltage should be rated at 2 kV to protect circuitry from static voltages
across connectors and cables. Each line-side center-tap should have its own decoupling cap to
chassis ground. Line-side center-taps must not be DC-shorted together.
MAC Interface Layout
Keep the signal lines as short as possible - no more than 6 to 9 inches; avoid “teeing” if at all
possible. Note that the 802.3 specification does not support the use of any external connectors on
the GMII Interface. The LXT1000’s GMII pads are designed to drive a 50 trace with a single 5 pf
load on the end.
Design the MAC Interface using external 42
close to the LXT1000 as is possible.
5V Tolerance Considerations
The inputs of the LXT1000 are 5V-compliant. These inputs tolerate 5V signal levels, even though
the device is powered to 3.3V. This applies to all digital input balls, and the inputs on the GMII
interface. Driving the GMII pads with 5V logic, however, may affect set-up and hold times, which
must be calculated at the 1.5V threshold of the GMII. The output balls on the MAC Interface meet
the electrical requirements for both the GMII and MII interfaces. The typical high output voltage
(2.6V) may not meet the switching requirements of some CMOS 5V logic.
“LXT1000 Operating Requirements” on page
series terminations. Place the series terminations as
Gigabit Ethernet Transceiver — LXT1000
64.
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