PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 135

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

4.7.4
4.7.4.1
4.7.4.2
4.7.4.3
4.7.4.4
4.7.5
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Figure 18. Serial MII Transmit Synchronization
CLOCK
TxSYNC
TX
Receive Data Stream
Receive data and control information are signalled in ten-bit segments. In 100 Mbps mode, each
segment contains a new byte of data. In 10 Mbps mode, each segment is repeated ten times (except
for the CRS bit), and the MAC can sample any of the ten segments.
Carrier Sense
The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS
bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10 sequential segments).
Receive Data Valid
The LXT9785/LXT9785E asserts the RX_DV bit (slot 1) when it receives a valid packet. The
assertion timing changes depending on line operating speed:
Receive Error
When the LXT9785/LXT9785E receives an invalid symbol from the network in 100BASE-TX
mode, it drives “0101” on the associated RxData signals.
Receive Status Encoding
The LXT9785/LXT9785E encodes status information onto the RxData line during IPG as seen in
Table 44 on page
(RxData<7:4> of the last byte of the previous frame). RxData and RX_DV are passed through the
internal elasticity FIFO to smooth any clock rate differences between the recovered clock and the
125 MHz reference clock.
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret COL
conditions using CRS and TxEN. CRS is unaffected by the transmit path.
•
•
For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first nibble of
preamble to the last nibble of the data packet.
For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with the
first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of
the packet.
TxER
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
TxEN
136. Status bit RxData<5> indicates the validity of the upper nibble
TXD0
TXD1
TXD2 TXD3 TXD4 TXD5 TXD6 TXD7
TxER
135