PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 202
PRLXT9785BC.D0 S L7WP
Manufacturer Part Number
PRLXT9785BC.D0 S L7WP
Description
Manufacturer
Intel
Datasheet
1.PRLXT9785BC.D0_S_L7WP.pdf
(234 pages)
Specifications of PRLXT9785BC.D0 S L7WP
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 84. Status Register (Address 1)
1. R = Read Only
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
Bit
6
5
4
3
2
1
0
Name
MF Preamble
Suppression
Auto-Negotiation
complete
Remote Fault
Auto-Negotiation
Ability
Link Status
Jabber Detect
Extended Capability
Description
0 = PHY will not accept management frames with
1 = PHY accepts management frames with preamble
0 = Auto-negotiation not complete
1 = Auto-negotiation complete
0 = No remote fault condition detected
1 = Remote fault condition detected
0 = PHY is not able to perform auto-negotiation
1 = PHY is able to perform auto-negotiation
0 = Link is down
1 = Link is up
0 = Jabber condition not detected
1 = Jabber condition detected
0 = Basic register capabilities
1 = Extended register capabilities
preamble suppressed
suppressed
Revision Date: 30-May-2006
Document Number: 249241
Type
Revision Number: 010
R/LH
R/LL
R/LL
R
R
R
R
1,2
Datasheet
Default
0
0
0
1
0
0
1
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