PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 145

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Figure 28. Protocol Sublayers
4.9.2.1.1 Preamble Handling
When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer
continues to encode the remaining RMII data until TxEN is de-asserted (see Table 46 on page 146).
It then returns to supplying IDLE symbols to the line driver.
The PCS layer performs the opposite function in the receive direction by substituting two preamble
nibbles for the SSD.
Sublayer
Sublayer
Sublayer
PMD
PMA
PCS
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785
De-scrambler
Scrambler/
100BASE-TX
Serializer/De-serializer
Link/Carrier Detect
Encoder/Decoder
MII Interface
Fiber Transceiver
100BASE-FX
LVPECL Interface
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