PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 190

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

190
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 51. RMII - 100BASE-TX Receive Timing
Table 72. RMII - 100BASE-TX Receive Timing Parameters
RxData<1:0>, CRS_DV, RXER setup to REFCLK
rising edge
RxData<1:0>, CRS_DV, RXER hold from REFCLK
rising edge
Receive start of /J/ to CRS_DV asserted
Receive start of /T/ to CRS_DV de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
testing.
100BASE-TX or 100BASE-FX).
RxData[1:0]
default configuration of 00 (32 bits of initial fill).
CRS_DV
REFCLK
3
3
TPFI
Parameter
t
3
Sym
t1
t2
t3
t4
t
1
Min
t
4
2
–
–
2
Typ
16
20
t
–
–
4
1
Max
14
14
21
27
Revision Date: 30-May-2006
Units
Document Number: 249241
BT
BT
ns
ns
2
2
Revision Number: 010
Conditions
Datasheet
Test
–
–
–
–