PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 148

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

148
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.3.6
4.9.3.7
Note:
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and
descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well
as receiving, polarity correction, and baseline wander correction functions.
4.9.3.6.1
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic
and test support.
4.9.3.6.2
The LXT9785/LXT9785E provides a baseline wander correction function which makes the device
robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is,
by definition, “unbalanced”. This means that the DC average value of the signal voltage can
“wander” significantly over short time intervals (tenths of seconds). This wander may cause
receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact
characteristics of the wander are completely data dependent.
The LXT9785/LXT9785E baseline wander correction characteristics allow the device to recover
error-free data while receiving worst-case “killer” packets over all cable lengths.
4.9.3.6.3
The LXT9785/LXT9785E automatically detects and corrects for the condition where the receive
signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four
inverted End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not
received by the maximum receive time-out period, the polarity state is reset to a non-inverted state.
Before the polarity switch occurs, every frame is inverted and causes RxER to assert. The specific
number of RxER events observed depends on how many link pulses occur between packets.
Fiber PMD Sublayer
The LXT9785/LXT9785E provides an LVPECL interface for connection to an external 3.3 V or
5 V fiber transceiver. (The external transceiver provides the PMD function for the optical medium.)
The LXT9785/LXT9785E uses a 125 Mbaud NRZI format for the fiber interface, and does not
support 10BASE-FL applications.
The BGA15 package does not support fiber interface.
4.9.3.7.1
The LXT9785/LXT9785E Signal Detect pins independently detect signal faults from the local
fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault
indications received from its link partner. The device “ORs” both fault conditions to set bit 1.4.
Register bit 1.4 is set once and clears when read.
Scrambler/Descrambler (100BASE-TX Only)
Baseline Wander Correction
Polarity Correction
Far End Fault Indications
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
Datasheet