PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 94

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 33. LED Signal Descriptions – BGA23 (Sheet 2 of 2)
Table 34. Power Supply Signal Descriptions – BGA23 (Sheet 1 of 2)
BGA23
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset.
4.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
G15,
H15,
H16,
F17,
J15,
J16,
G17
H17
F16
BGA23
Ball/Pin Designation
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
Designation
G13,
C11,
J14,
D14
L13
A2,
A8,
C1,
F5,
L5,
J5
Ball/Pin
PQFP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
185
186
187
189
190
191
192
193
194
PQFP
184,
196
208
164
65,
78,
18,
29,
47,
56,
98,
LED5_1_L
LED5_2_L
LED5_3_L
LED6_1_L
LED6_2_L
LED6_3_L
LED7_1_L
LED7_2_L
LED7_3_L
Symbol
VCCPECL
Symbol
VCCIO
VCCD
OD, TS, SL,
OD, TS, SL,
OD, TS, SL,
Type
Type
IP
IP
IP
–
–
–
1
Signal Description
Digital Power Supply - Core.
+2.5 V supply for core digital circuits.
Digital Power Supply - I/O Ring.
+2.5/3.3 V supply for digital I/O circuits. The digital
input circuits running off of this rail, having a TTL-level
threshold and over-voltage protection, may be
interfaced with 3.3/5.0 V, when the IO supply is 3.3 V,
and 2.5/3.3/5.0 V when 2.5 V.
Digital Power Supply - PECL Signal Detect Inputs.
+2.5/3.3 V supply for PECL Signal Detect input
circuits. If Fiber Mode is not used (that is, G_FX/TP_L
is pulled Low), the VCCPECL pins may be tied to
GNDPECL to save power.
Signal Description
Port 5 LED Drivers 1-3.
These pins drive LED indicators for Port 5. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to
Hex 14)” on page 213
Port 6 LED Drivers 1-3.
These pins drive LED indicators for Port 6. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to
Hex 14)” on page 213
Port 7 LED Drivers 1-3.
These pins drive LED indicators for Port 7. Each LED
can display one of several available status conditions
as selected by the LED Configuration Register (refer
to
Hex 14)” on page 213
Table 96 “LED Configuration Register (Address 20,
Table 96 “LED Configuration Register (Address 20,
Table 96 “LED Configuration Register (Address 20,
2,3
for details).
for details).
for details).
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