PRLXT9785BC.D0 S L7WP Intel, PRLXT9785BC.D0 S L7WP Datasheet - Page 89

• Manufacturer Part Number: PRLXT9785BC.D0 S L7WP
• Manufacturer: Intel

Specifications of PRLXT9785BC.D0 S L7WP

• Lead Free Status / RoHS Status: Compliant

89
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet 1 of 4)
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
3. The LINKHOLD ability is available only for stepping 4 (Revision D0).
BGA23
M15
L14
N3,
M4
D5
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Designation
Ball/Pin
PQFP
174
175
94
93
50
TxSLEW_0
TxSLEW_1
PWRDWN
RESET_L
Symbol
PAUSE
ID, I, ST
I, ST, ID
I, ST, ID
I, ST, IP
Type
1
Signal Description
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read
and overwritten after startup / reset.
These pins select the TX output slew rate for all ports
(rise and fall time) as follows:
TxSLEW_1
Pause Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 4.10 for
all ports. This register bit can be read and overwritten
after startup / reset.
When High, the LXT9785/9785E advertises Pause
capabilities on all ports during auto-negotiation.
This pin is shared with RMII-RxER1. An external pull-
up resistor (see applications section for value) can be
used to set Pause active while RxER1 is three-stated
during H/W reset. If no pull-up is used, the default
Pause state is set inactive via the internal pull-down
resistor.
Power-Down.
When High, forces the LXT9785/9785E into global
power-down mode.
Pin is not on JTAG chain.
Reset.
This active low input is ORed with the control register
Reset Register bit 0.15. When held Low, all outputs are
forced to inactive state.
Pin is not on JTAG chain.
0
0
1
1
TxSLEW_0
0
1
0
1
2
Slew Rate (Rise and Fall
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
Time)
3.3 ns
3.6 ns
3.9 ns
4.2 ns
Datasheet