HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet
HBLXT9763HC.C4
Specifications of HBLXT9763HC.C4
Related parts for HBLXT9763HC.C4
HBLXT9763HC.C4 Summary of contents
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... LXT9763 Fast Ethernet 10/100 Hex Transceiver with Full MII The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock recovery with proprietary Optimal Signal Processing (OSP™) architecture improves SNR 3 dB over ideal analog filters ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Functional Description 1.1 Introduction..........................................................................................................16 1.1.1 OSP™ Architecture ................................................................................16 1.1.2 Comprehensive Functionality .................................................................16 1.2 Interface Descriptions..........................................................................................17 1.2.1 10/100 Network Interface .......................................................................17 1.2.2 Twisted-Pair Interface ............................................................................17 1.2.3 Fiber Interface ........................................................................................18 1.2.4 Configuration Management Interface .....................................................18 1.2.5 MDIO Management Interface .................................................................18 ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 1.13.4 Boundary Scan Register ........................................................................ 37 2.0 Application Information 2.1 Design Recommendations .................................................................................. 38 2.1.1 General Design Guidelines .................................................................... 38 2.1.2 Power Supply Filtering ........................................................................... 38 2.1.3 Power and Ground ...
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... Auto Negotiation and Fast Link Pulse Timing ....................................................55 31 Fast Link Pulse Timing .......................................................................................56 32 MDIO Write Timing (MDIO Sourced by MAC) ....................................................56 33 MDIO Read Timing (MDIO Sourced by PHY) ....................................................57 34 Power-Up Timing ................................................................................................57 35 RESET And Power-Down Recovery Timing ......................................................58 36 PHY Identifier Bit Mapping .................................................................................64 37 LXT9763 Package Specification ...
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... Register Bit Map.................................................................................................. 60 38 Control Register (Address 0)............................................................................... 62 39 Status Register (Address 1) ................................................................................ 62 40 PHY Identification Register 1 (Address 2)........................................................... 63 41 PHY Identification Register 2 (Address 3)........................................................... 64 42 Auto Negotiation Advertisement Register (Address 4)........................................ 64 43 Auto Negotiation Link Partner Base Page Ability Register (Address 5) .............. 65 44 Auto Negotiation Expansion (Address 6) ............................................................ 66 45 Auto Negotiation Next Page Transmit Register (Address 7) ...
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Interrupt Status Register (Address 19, Hex 13) ..................................................70 51 LED Configuration Register (Address 20, Hex 14)..............................................71 52 Transmit Control Register #1 (Address 28).........................................................72 53 Transmit Control Register #2 (Address 30).........................................................72 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII ...
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Revision History Revision Date Description ...
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Figure 1. LXT9763 Block Diagram RESET CFG<2:0> Management / ADD<4:0> Mode Select MDIO Logic MDC MDINT Register Set TX_ENn TXDn_<3:0> Parallel/Serial TX_ERn Converter TX_CLKn Register Set ED/CFGn_<3:0> Collision COLn Detect RX_CLKn Serial to RXDn_<3:0> Parallel RXDVn Converter Carrier Sense CRSn ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 2. LXT9763 Pin Assignments GNDD ....... 1 RX_ER4/RXD4_4 ....... 2 TX_ER4/TXD4_4 ....... 3 TX_CLK4 ....... 4 TX_EN4 ....... 5 TXD4_0 ....... 6 TXD4_1 ....... 7 TXD4_2 ....... 8 TXD4_3 ...
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Table 1. LXT9763 MII Signal Descriptions Pin# Symbol Type 79 TXD0_0 82 TXD0_1 I 83 TXD0_2 84 TXD0_3 60 TXD1_0 61 TXD1_1 I 62 TXD1_2 63 TXD1_3 42 TXD2_0 43 TXD2_1 I 44 TXD2_2 45 TXD2_3 24 TXD3_0 25 TXD3_1 ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 1. LXT9763 MII Signal Descriptions (Continued) Pin# Symbol Type 51 RXD1_0 50 RXD1_1 O 49 RXD1_2 48 RXD1_3 35 RXD2_0 34 RXD2_1 O 33 RXD2_2 30 RXD2_3 17 RXD3_0 ...
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... MII Control Interface Pins Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When bit 18 active Low output on this pin indicates status change. Interrupt is cleared by reading Register 19. ...
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... Type Column Coding Input Output Analog weak internal pull-up weak internal pull-down Signal Description Address <4:0>. Sets base address. Each port adds its port number to this address to determine its PHY address. Port 0 Address = Base + 0. Port 1 Address = Base + 1. Port 2 Address = Base + 2. Port 3 Address = Base + 3. ...
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Table 6. LXT9763 LED Signal Descriptions 1 Pin# Symbol Type 181 LED/CFG0_1 182 LED/CFG0_2 I/OD/OS 183 LED/CFG0_3 176 LED/CFG1_1 I/OD/OS 177 LED/CFG1_2 180 LED/CFG1_3 173 LED/CFG2_1 174 LED/CFG2_2 I/OD/OS 175 LED/CFG2_3 170 LED/CFG3_1 I/OD/OS 171 LED/CFG3_2 172 LED/CFG3_3 162 LED/CFG4_1 ...
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... LXT9763 also supports 100BASE-FX operation via a Pseudo-ECL (PECL) interface. 1.1.1 OSP™ Architecture Intel’s LXT9763 incorporates high-efficiency Optimal Signal Processing™ design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much over an ideal all-analog equalizer ...
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Interface Descriptions Figure 3. LXT9763 Interfaces MII Data I/F MII Mgmt I/F Hardware Control I/F & Port LEDs 1.2.1 10/100 Network Interface The LXT9763 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII internal impedance is high enough that it has no practical effect on the external termination circuit. On the transmit side, Intel’s patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to the designer to match the output waveform to the magnetic characteristics ...
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... PHY ADDR (BASE+1) Port 1 ex. 5 PHY ADDR (BASE+2) Port 2 ex. 6 PHY ADDR (BASE+3) Port 3 ex. 7 PHY ADDR (BASE+4) Port 4 ex. 8 PHY ADDR (BASE+5) Port 5 ex. 9 1.3.0.1 MII Interrupts The LXT9763 provides a single interrupt pin available to all ports. Interrupt logic is shown in Figure 7 ...
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... The LXT9763 requires four power supply inputs, VCCD, VCCR, VCCT, and VCCIO. The digital and analog circuits require 3.3 V supplies (VCCD, VCCR and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground PHY Address Register Address Write OR AND Interrupt Enable “Hardware Configuration Settings” on page 23 D15 D14 D1 D0 ...
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An additional supply may be used for the MII (VCCIO). same power source used to supply the controller on the other side of the MII interface. Refer to Table 17 on page matter of good practice, these ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 1.6.1 Power-Down Mode The LXT9763 provides a per-port Power-Down Mode. Individual port power-down control is provided by bit 0.11 in the respective port Control Registers (refer to individual port power-down, ...
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Hardware Configuration Settings The LXT9763 provides a hardware option to set the initial device configuration. The hardware option uses the three LED/CFG pins for each port. This provides three control bits per port, as listed in Table 7. The ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 1.8 Establishing Link See Figure 10 for an overview of link establishment. 1.8.1 Auto-Negotiation The LXT9763 attempts to auto-negotiate with its counter-part across the link by sending Fast Link Pulse ...
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Figure 10. Overview of Link Establishment Disable Auto-Negotiation Go To Forced Settings Done 1.9 MII Operation Figure simple block diagram of the MII data interface. Separate channels are provided for transmitting data from the MAC to the ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 11. MII Data Interface Media Access Controller (MAC) 1.9.1 Transmit Clock The LXT9763 is the master clock source for data transmission. It automatically sets the speed of TX_CLK to ...
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Carrier Sense Carrier sense (CRS asynchronous output always generated when a packet is received from the network and in some modes when a packet is transmitted. On transmit, CRS is asserted Mbps ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 8. Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition Full-Duplex 100 Mbps Half-Duplex Full-Duplex 10 Mbps Half-Duplex, 16 Half-Duplex, 16 Test Loopback is ...
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... PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. (For symbol mode operation, the 4B/5B function can be bypassed by setting 16.11 = 1.) For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter (SSD), for the first two nibbles received across ...
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Table 9. 4B/5B Coding (Continued) 4B Code Code Type Name DATA ...
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... RXD outputs zeros until the received data is decoded and available for transfer to the controller. 1.10.2.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. ...
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The scrambler/descrambler can be bypassed by setting bit 16. The scrambler is automatically bypassed when the fiber port is enabled. Scramber bypass is provided for diagnostic and test support. Baseline Wander Correction (100TX Only) The LXT9763 provides a ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII The LXT9763 does not support fiber connections at 10 Mbps. 1.11.1 10T Preamble Handling The LXT9763 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when ...
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Monitoring Operations 1.12.1 Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: • Bit 17.7 is set to 1 once the auto-negotiation process is completed. • Bits 1.2 and 17.10 are set to 1 once the link is established. • ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 1.12.2.1 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, ...
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... Version Part ID (hex) 0000 2623 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110) which becomes 111 1110. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Description Capture Shift Update ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 2.0 Application Information 2.1 Design Recommendations The LXT9763 is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. To achieve maximum ...
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... Intel recommends filtering the power supply to the analog VCC pins of the LXT9763. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9763, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 2.1.5 The RBIAS Pin The LXT9763 requires a 22.1 k ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin ...
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Table 13. Magnetics Requirements Parameter Return Loss Rise Time 2.2 Typical Application Circuits Figure 18 shows a typical layout of the LXT9763 twisted-pair interface in a dual-high (stacked) RJ-45 application. Figure 17. Power and Ground Supply Connections LXT9763 GNDS RBIAS ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 18. Typical Twisted-Pair Interface A LXT9763 1. The 100 transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive pair center-tap do not ...
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Figure 19. Typical Fiber Interface 50 TPFONn TPFOPn LXT9763 TPFINn TPFIPn 1. Refer to fiber transceiver manufacturer’s recommendations for termination circuitry. Example shown above is suitable for HFBR5900-series devices. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 3.0 Test Specifications Note: Table 14 through Table 34 specifications of the LXT9763. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in ...
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Table 17. Digital I/O Characteristics - MII Pins Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Driver output resistance (Line driver output enabled) 1. Typical values are at 25 °C and are for ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 20. 100BASE-FX Transceiver Characteristics Parameter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are ...
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Figure 20. 100BASE-TX Receive Timing (4B Mode) TPFI CRS RX_DV RXD<3:0> RX_CLK COL Table 22. 100BASE-TX Receive Timing Parameters (4B Mode) Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 21. 100BASE-TX Transmit Timing (4B Mode) 0ns TX_CLK TX_EN TXD<3:0> TPFO CRS Table 23. 100BASE-TX Transmit Timing Parameters (4B Mode) Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, ...
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Figure 22. 100BASE-TX Receive Timing (5B Mode) TPFI TPFI CRS CRS RX_DV RX_DV RXD<4:0> RXD<4:0> RX_CLK RX_CLK COL COL Table 24. 100BASE-TX Receive Timing Parameters (5B Mode) Parameter RXD<4:0>, RX_DV, RX_ER setup to RX_CLK High RXD<4:0>, RX_DV, RX_ER hold from ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 23. 100BASE-TX Transmit Timing (5B Mode) 0ns TX_CLK TX_EN TXD<4:0> TPFO CRS Table 25. 100BASE-TX Transmit Timing Parameters (5B Mode) Parameter TXD<4:0>, TX_EN, TX_ER setup to TX_CLK High TXD<4:0>, ...
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Figure 24. 100BASE-FX Receive Timing TPFI CRS RX_DV RXD<3:0> RX_CLK COL Table 26. 100BASE-FX Receive Timing Parameters Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 25. 100BASE-FX Transmit Timing 0ns TXCLK TX_EN TXD<3:0> t5 TPFO t3 CRS Table 27. 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER ...
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Figure 26. 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS t 6 TPFI t 8 COL Table 28. 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER setup to RX_CLK High RXD, RX_DV, RX_ER hold from RX_CLK High TPFI in to ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 27. 10BASE-T Transmit Timing TX_CLK t 1 TXD, TX_EN, TX_ER t 3 CRS TPFO Table 29. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, ...
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Table 30. 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) delay after TX_EN off COL (SQE) pulse duration 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Figure ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 31. Fast Link Pulse Timing FLP Burst TPFOP t4 Table 32. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock ...
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... Figure 33. MDIO Read Timing (MDIO Sourced by PHY) MDC MDIO Table 33. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 35. RESET And Power-Down Recovery Timing RESET MDIO,etc Table 35. RESET and Power-Down Recovery Timing Parameters Parameter RESET pulse width RESET recovery delay 1. Typical values are at 25° ...
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... Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto- Negotiation” sections of the IEEE 802.3 specification. • Additional registers (16 through 30) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 60 Datasheet ...
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Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 61 ...
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... PHY not able to perform 100BASE-T4. 100BASE-X Full PHY able to perform full-duplex 100BASE-X. 1.14 Duplex 0 = PHY not able to perform full-duplex 100BASE-X. 100BASE-X Half PHY able to perform half-duplex 100BASE-X. 1.13 Duplex 0 = PHY not able to perform half-duplex 100BASE- Read Only Latching Low. ...
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... Table 39. Status Register (Address 1) (Continued) Bit Name 1 = PHY able to operate at 10 Mbps in full-duplex mode. 1.12 10 Mbps Full-Duplex 0 = PHY not able to operate at 10 Mbps full-duplex mode PHY able to operate at 10 Mbps in half-duplex mode. 1.11 10 Mbps Half-Duplex 0 = PHY not able to operate at 10 Mbps in half-duplex. ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 41. PHY Identification Register 2 (Address 3) Bit Name The PHY identifier composed of bits 19 through 24 of the 3.15:10 PHY ID number OUI. Manufacturer’s 3.9:4 6 bits containing manufacturer’s part number. model number Manufacturer’s 3.3:0 4 bits containing manufacturer’ ...
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Table 42. Auto Negotiation Advertisement Register (Address 4) (Continued) Bit Name 1 = 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT9763 does not support 100BASE-T4 but allows this bit to be set to 4.9 100BASE-T4 ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 43. Auto Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit Name 10BASE Link Partner is 10BASE-T full-duplex capable. 5 Link Partner is ...
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Table 45. Auto Negotiation Next Page Transmit Register (Address 7) Bit Name Next Page 1 = Additional next pages follow. 7.15 (NP Last page. 7.14 Reserved Write as 0, ignore on read. Message Page 1 = Message page. ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 47. Port Configuration Register (Address 16, Hex 10) Bit Name 16.15 Reserved Write as zero, ignore on read Force Link Pass. Sets appropriate registers, state machines and ...
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Table 48. Quick Status Register (Address 17, Hex 11) (Continued) Bit Name 1 = Link is up. 17.10 Link 0 = Link is down Full-duplex. 17.9 Duplex Mode 0 = Half-duplex LXT9763 is in Auto-Negotiation Mode. ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 49. Interrupt Enable Register (Address 18, Hex 12) (Continued) Bit Name 18.2 Reserved Write as 0, ignore on read. Interrupt Enable. 18.1 INTEN 1 = Enable interrupts on this ...
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Table 51. LED Configuration Register (Address 20, Hex 14) Bit Name 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link ...
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LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 51. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name 00 = Stretch LED events Stretch LED events to 60 ms. 20.3:2 LEDFREQ ...
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Package Specifications Figure 37. LXT9763 Package Specification 208-Pin Plastic Quad Flat Package • Part Number LXT9763HC • Commercial Temperature Range ( Datasheet Fast Ethernet 10/100 ...
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