HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 30

• Manufacturer Part Number: HBLXT9763HC.C4
• Manufacturer: Intel

Specifications of HBLXT9763HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
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1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
Code Type
Figure 15. Protocol Sublayers
Table 9.
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following
then returns to supplying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD.
Dribble Bits
The LXT9763 handles dribbles bits in all modes. If between 1-4 dribble bits are received, the
nibble is passed across the MII, padded with 1s if necessary. If between 5-7 dribble bits are
received, the second nibble is not sent onto the MII bus
4B/5B Coding
4B Code
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
Sublayer
Sublayer
Sublayer
PMA
PMD
PCS
Name
0
1
2
3
LXT9763
De-scrambler
Scrambler/
5B Code
4 3 2 1 0
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
100BASE-TX
Serializer/De-serializer
Link/Carrier Detect
Encoder/Decoder
Table 9 on page
Data 0
Data 1
Data 2
Data 3
MII Interface
Fiber Transceiver
30, until TX_EN is de-asserted. It
Interpretation
100BASE-FX
PECL Interface
Datasheet