HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 22

• Manufacturer Part Number: HBLXT9763HC.C4
• Manufacturer: Intel

Specifications of HBLXT9763HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
1.6.1
1.6.2
22
Figure 8. Initialization Sequence
Power-Down Mode
The LXT9763 provides a per-port Power-Down Mode. Individual port power-down control is
provided by bit 0.11 in the respective port Control Registers (refer to
individual port power-down, the following conditions are true:
Reset
The LXT9763 provides both hardware and software resets. Configuration control of Auto-
Negotiation, speed and duplex mode selection is handled differently for each. During a hardware
reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to Table 7 on page 23 for
pin settings and Table 38 on page 62 for register bit definitions).
During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset will not be detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
•
•
•
The individual port is shut down.
The MDIO registers remain accessible.
The MDIO registers are unaffected.
No
Read H/W Control Interface
Initialize MDIO Registers
Pass Control to MDIO
Power-up or Reset
Reset
?
Yes
Table 38 on page
62). During
Datasheet