HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 13

• Manufacturer Part Number: HBLXT9763HC.C4
• Manufacturer: Intel

Specifications of HBLXT9763HC.C4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
1. Type Column Coding: I = Input, O = Output.
1. Type Column Coding: I = Input, O = Output, A = Analog.
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
108, 109
124, 125
137, 136
148, 149
153, 152
104, 105
120, 121
141, 140
144, 145
157, 156
113, 112
117, 116
Pin#
95
96
90
where X is the register number (0-32) and Y is the bit number (0-15).
where X is the register number (0-32) and Y is the bit number (0-15).
Pin#
Table 1. LXT9763 MII Signal Descriptions (Continued)
Table 2. LXT9763 Network Interface Signal Descriptions
Table 3. LXT9763 Miscellaneous Signal Descriptions
Pin#
91
94
93
MDC
MDIO
MDINT
TPFOP0, TPFON0
TPFOP1, TPFON1
TPFOP2, TPFON2
TPFOP3, TPFON3
TPFOP4, TPFON4
TPFOP5, TPFON5
TPFIP0, TPFIN0
TPFIP1, TPFIN1
TPFIP2, TPFIN2
TPFIP3, TPFIN3
TPFIP4, TPFIN4
TPFIP5, TPFIN5
Symbol
TxSLEW_0
TxSLEW_1
RESET
Symbol
Symbol
Type
Type
OD
I/O
I
I
I
Type
1
1
O
I
Management Data Clock. Clock for the MDIO serial data channel.
Maximum frequency is 8 MHz.
Management Data Input/Output. Bidirectional serial data channel for PHY/STA
communication.
Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin
indicates status change. Interrupt is cleared by reading Register 19.
1
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate
(rise and fall time) as follows:
TxSLEW_1
Reset. This active Low input is OR’ed with the control register Reset bit (0.15).
When held Low, output pins go to inactive state.
Twisted-Pair/Fiber Outputs, Positive & Negative - Ports 0-5.
During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3
compliant pulses onto the line.
During 100BASE-FX operation, TPFO pins produce differential PECL outputs
for fiber transceivers.
Twisted-Pair/Fiber Inputs, Positive & Negative - Ports 0-5.
During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential
100BASE-TX or 10BASE-T signals from the line.
During 100BASE-FX operation, TPFI pins receive differential PECL inputs
from fiber transceivers.
MII Control Interface Pins
0
0
1
1
TxSLEW_0
0
1
0
1
Signal Description
Signal Description
Signal Description
Slew Rate (Rise and Fall Time)
2.5 ns
3.1 ns
3.7 ns
4.3 ns
2
2
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