HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 25
HBLXT9763HC.C4
Manufacturer Part Number
HBLXT9763HC.C4
Description
Manufacturer
Intel
Datasheet
1.HBLXT9763HC.C4.pdf
(74 pages)
Specifications of HBLXT9763HC.C4
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Datasheet
Figure 10. Overview of Link Establishment
MII Operation
Figure 11
transmitting data from the MAC to the LXT9763 (TXD), and for passing data received from the
line to the MAC (RXD). Each channel has its own clock, data bus, and control signals. Nine signals
are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL and
CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and
TX_ER. The LXT9763 supplies both transmit and receive clock signals as well as separate outputs
for carrier sense and collision.
Data is normally exchanged across the MII in 4-bit-wide nibbles. However, two alternative data
exchange methods are provided. A 5-bit symbol mode is available via bit 16.11 for 100M
operation. Refer to
Auto-Negotiation
Go To Forced
Disable
Settings
is a simple block diagram of the MII data interface. Separate channels are provided for
Done
Table 47 on page 68
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
0.12 = 0
Power-Up, Reset,
Link Failure
Check Value
Attempt Auto-
Start
0.12
for additional information on these bit settings.
Negotiation
0.12 = 1
YES
Listen for 100TX
Auto-Neg/Parallel Detection
Idle Symbols
Link Set
Enable
NO
Listen for 10T
Link Pulses
25
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