PEB3265FV15XP Infineon Technologies, PEB3265FV15XP Datasheet - Page 62
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PEB3265FV15XP
Manufacturer Part Number
PEB3265FV15XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB3265FV15XP.pdf
(383 pages)
Specifications of PEB3265FV15XP
On-hook Transmission
Yes
Polarity Reversal
Yes
On-chip Ring Relay Driver
Yes
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TQFP
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Lead Free Status / RoHS Status
Compliant
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Preliminary
3.7.2
SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual
polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching
the REVPOL bit in register BCR1 to one or switching to the “Active with Metering” mode
by the CIDD or CIOP command (see
Page
3.7.2.1
Some applications require a smooth polarity reversal (soft reversal), as shown in
Figure
reversal is deactivated by the SOFT-DIS bit in register BCR2.
Figure 30
START: The soft ramp starts by setting the REVPOL bit in register BCR1 to 1. The DC
characteristic is switched off.
SR-END1: At the soft reversal end one point, the DC characteristic is switched on again.
Programmable by the DuSLICOS software, e.g. U/8.
SR-END2: At the soft reversal end two point, the soft ramp is switched off.
Programmable by the DuSLICOS software, e.g. 1/16
From START to SR-END2 the READY bit in register INTREG2 is set to 0 (see register
description in
Data Sheet
SOFT-DIS = 1
SOFT-DIS = 0
78).
30. Soft reversal helps to prevent negative effects like non-required ringing. Soft
Metering by Polarity Reversal
Soft Reversal
Chapter 6.3.1.2
Soft Reversal (Example for Open Loop)
Immediate reversal is performed (hard reversal)
Soft reversal is performed. Transition time (time from START to SR-
END1, see
default value 80 ms.
V
TIP/RING
-10
-15
-20
-25
2 5
2 0
1 5
1 0
-5
5
0
0
[V]
U
START
5 0
Figure
for further information).
U/8
“Operating Modes for the DuSLIC Chip Set” on
1 00
30) is programmable by CRAM coefficients,
SR-END1
62
150
2 00
SR-END1.
SR-END2
= 1/16*SR-END1
250
Functional Description
t [ms]
ezm14038.wmf
2000-07-14
DuSLIC
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