PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet - Page 121

14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan

PIC16LF1847-E/ML

Manufacturer Part Number
PIC16LF1847-E/ML
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet

Specifications of PIC16LF1847-E/ML

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
32 MHz
Data Ram Size
256 B
Number Of Programmable I/os
15
Number Of Timers
ÿ4 x 8-bit, 1 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
Through Hole
Interface Type
SPI, I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
12.2
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA5, which is
input only and its TRIS bit will always read as ‘1’.
Example 12-1
Reading the PORTA register
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
The TRISA register
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
EXAMPLE 12-1:
12.2.1
Each of the PORTA pins has an individually configurable
internal weak pull-up. Control bit WPUA<5> enables or
disables the pull-up (see
pull-up is automatically turned off when the port pin is
configured as an output. The pull-up is disabled on a
Power-on
OPTION_REG register.
 2011 Microchip Technology Inc.
BANKSEL PORTA
CLRF
BANKSEL LATA
CLRF
BANKSEL ANSELA
CLRF
BANKSEL TRISA
MOVLW
MOVWF
Note:
PORTA Registers
12-4). Setting a TRISA bit (= 1) will make the
PORTA
LATA
ANSELA
0Ch
TRISA
The ANSELA register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
WEAK PULL-UPS
Reset
shows how to initialize PORTA.
by
INITIALIZING PORTA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<3:2> as inputs
;and set RA<7:4,1:0>
;as outputs
(Register
the
Register
(Register
WPUEN
12-4) controls the
12-6). The weak
12-3) reads the
bit
of
Preliminary
the
12.2.2
The ANSELA register
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
The TRISA register
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Note:
ANSELA REGISTER
The ANSELA register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
PIC16(L)F1847
(Register
(Register
12-4) controls the PORTA
12-7) is used to
DS41453B-page 121

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