PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet - Page 225

• Manufacturer Part Number: PIC16LF1847-E/ML
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16LF1847-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad
• Core: PIC
• Processor Series: PIC16LF
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 MHz
• Data Ram Size: 256 B
• Number Of Programmable I/os: 15
• Number Of Timers: ÿ4 x 8-bit, 1 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: Through Hole
• Interface Type: SPI, I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.6
In Single Output mode, PWM steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once
(CCPxM<3:2> = 11
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STRx<D:A> bits of the
PSTRxCON register, as shown in
While the PWM Steering mode is active, CCPxM<1:0>
bits of the CCPxCON register select the PWM output
polarity for the Px<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in
“Enhanced
auto-shutdown event will only affect pins that have
PWM outputs enabled.
FIGURE 24-18:
 2011 Microchip Technology Inc.
Note 1: Port outputs are configured as shown when
Note:
PORT Data
PORT Data
PORT Data
PORT Data
PxA Signal
CCPxM0
CCPxM1
CCPxM0
2: Single PWM output requires setting at least
CCPxM1
the
STRxA
STRxB
STRxC
STRxD
the CCPxCON register bits PxM<1:0> = 00
and CCPxM<3:2> = 11.
one of the STRx bits.
PWM STEERING MODE
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
Single
PWM
and
Auto-shutdown
SIMPLIFIED STEERING
BLOCK DIAGRAM
Output
1
0
1
0
1
0
1
0
PxM<1:0> = 00
mode
Register
TRIS
TRIS
TRIS
TRIS
Section 24.4.3
PxB pin
PxC pin
PxD pin
is
mode”.
PxA pin
24-5.
selected
of
Preliminary
the
An
24.4.6.1
The STRxSYNC bit of the PSTRxCON register gives
the user two selections of when the steering event will
happen. When the STRxSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the
output signal at the Px<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRxSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figure 24-19
diagrams of the PWM steering depending on the
STRxSYNC setting.
24.4.7
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (PxA/PxC and PxB/PxD). The PWM output
polarities must be selected before the PWM pin output
drivers
configuration while the PWM pin output drivers are
enable is not recommended since it may result in
damage to the application circuits.
The PxA, PxB, PxC and PxD output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMRxIF bit of the PIRx register
being set as the second PWM period begins.
Note:
are
START-UP CONSIDERATIONS
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external cir-
cuits must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
Steering Synchronization
and
PIC16(L)F1847
enabled.
Figure 24-20
Changing
illustrate the timing
DS41453B-page 225
the
polarity