TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 19

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 10.
Legend: * = default value
TDA9955HL_1
Product data sheet
Address Register
11h
12h
PLL_MNDIV_MSB
PLL_NDIV_LSB
PLL_MNDIV registers (address 11h and 12h) bit description
9.2.5 Pixel clocks generation registers
Table 11.
Legend: * = default value
Table 12.
Legend: * = default value
Bit
7 to 2
1
0
Bit
7 to 5 -
4 to 0 PHASE[4:0]
Symbol
Bit
7 to 6 MDIV[1:0]
5 to 4 -
3 to 0 NDIV[11:8]
7 to 0 NDIV[7:0]
Symbol
-
x
PLL_LOCK
LOCKFLAG register (address 13h) bit description
DLL_PHASE register (address 14h) bit description
Symbol
Access Value
W
W
Access Value
W
W
R
Rev. 01 — 17 March 2008
Access Value Description
W
W
W
W
000*
1 0000* phase: these bits set the phase shift for the three clock
00 0000* not used
0*
0*
1
Triple 8-bit analog-to-digital video converter for HDTV
00
01
10
11*
00*
3h*
60h*
Description
not used
signals CLKPIX, CLKFOR and CLKOUT; it is the fine
adjustment of the phase, see
Description
for test; must be set to default value for proper
operation
PLL_lock: indicates when the PLL is locked
not locked
locked
master divider: selects the master divider to
adjust the sampling frequency range with the PLL
frequency range from 110 MHz to 200 MHz
not used
pixel divider: pixel division value
divided by 1; > 110 Msample/s
divided by 2; 50 Msample/s to 110 Msample/s
divided by 4; 25 Msample/s to < 50 Msample/s
divided by 8; 12.5 Msample/s to < 25 Msample/s
TDA9955HL
Table 15
© NXP B.V. 2008. All rights reserved.
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