TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 35

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 44.
[1]
TDA9955HL_1
Product data sheet
Codeword
3FFh
000h
000h
SAV/EAV
F = 0 during field 1; F = 1 during field 2; V = 1 during field blanking; V = 0 elsewhere; H = 0 in SAV, H = 1 in EAV and P0 to P3 are
protection bits.
[1]
Timing reference codes
9.2.14 Output formatter register
A9
1
0
0
1
Table 43.
Legend: * = default value
[1]
[2]
[3]
Bit
7
6
5
4
3
2
1 and 0 FOR_SEL[1:0] W
In 4 : 4 : 4, the video is output on three video ports, one per color.
In 4 : 2 : 2 semi-planar, the video is output on two video ports, one for luminance (Y) and one for
chrominance (C
In 4 : 2 : 2 ITU-R BT.656, the video is output on one video port (C
A8
1
0
0
F
Symbol
OUT
VPL
-
BLC
TRC
-
OF_CTRL register (address E5h) bit description
B
A7
1
0
0
V
and C
Rev. 01 — 17 March 2008
R
Access Value Description
W
W
W
W
W
W
alternately).
A6
1
0
0
H
Triple 8-bit analog-to-digital video converter for HDTV
0*
1
0
1*
-
0*
1
0*
1
0*
00
01
10*
11
A5
1
0
0
P3
output control: sets the outputs (VPA[11:0],
VPB[11:0], VPC[11:0], VCLK, HS, VS, CS, HREF,
VREF, FREF, DE, OR_R, OR_B, OR_G, CTL0 to
CTL3, PL)
video ports LOW
not used
blanking codes
timing reference codes
for test; must be set to logic 0 for proper operation
formatter selection
outputs active
outputs high-impedance
forces the unused video port outputs to
high-impedance
forces the unused video port outputs to LOW
inserts the blanking codes
removes the blanking codes
inserts the timing reference codes; the signals HREF
and VREF must be programmed into the VHREF
timing generator to insert the timing reference codes;
timing reference codes are inserted in all video port
streams and are present during the vertical blanking;
see
removes the timing reference codes
4 : 4 : 4 format
4 : 2 : 2 semi-planar format
4 : 2 : 2 ITU-R BT.656 format
undefined
A4
1
0
0
P2
Table 44
A3
1
0
0
P1
[1]
B
-Y-C
R
-Y sequence).
A2
1
0
0
P0
TDA9955HL
[2]
[3]
© NXP B.V. 2008. All rights reserved.
A1
1
0
0
0
A0
1
0
0
0
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