TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 30

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 34.
Legend: * = default value
TDA9955HL_1
Product data sheet
Addr Register
BFh
C0h
C1h
Fig 6.
FREF_F1_S_LSB 7 to 0 FREF_F1_START[7:0]
FREF_POL_MSB 7
FREF_F2_S_LSB 7 to 0 FREF_F2_START[7:0]
pixel 1
HREF
HREF and VREF in progressive case
line 1
Field reference registers (address BFh to C1h) bit description
(1)
blanking
HREF_START[11:0]
period
Bit
6 to 4 FREF_F1_START[10:8] W
3
2 to 0 FREF_F2_START[10:8] W
Symbol
FPOL
-
HIGH during active video;
LOW during horizontal blanking period
active video
Rev. 01 — 17 March 2008
Triple 8-bit analog-to-digital video converter for HDTV
Access Value Description
W
W
W
W
HREF_END[11:0]
00h*
0*
1
000*
0*
000*
00h*
VREF
field reference for field 1 start (LSB): index
of the first line for field 1 which corresponds to
the line where the FREF signal toggles, see
register FREF_POL_MSB bit 6 to bit 4
field polarity: defines the polarity of the
FREF signal and bit F in the SAV/EAV code
field reference for field 1 start (MSB): index
of the first line for field 1 which corresponds to
the line where the FREF signal toggles, see
register FREF_F1_S_LSB bit 7 to bit 0
not used
field reference for field 2 start: index of the
first line for field 2 which corresponds to the
line where the FREF signal toggles
field 1 is LOW and field 2 is HIGH
field 1 is HIGH and field 2 is LOW
VREF_F1_WIDTH[7:0]
LOW during active video;
HIGH during vertical blanking period
VREF_F2 registers must be set to 0
VREF changes state at pixel 1
VREF_F1_START[10:0]
VREF_F1_WIDTH[7:0]
TDA9955HL
© NXP B.V. 2008. All rights reserved.
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