TMC22152KHC Fairchild Semiconductor, TMC22152KHC Datasheet

no-image

TMC22152KHC

Manufacturer Part Number
TMC22152KHC
Description
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of TMC22152KHC

Screening Level
Commercial
Package Type
MQFP
Pin Count
100
Lead Free Status / RoHS Status
Compliant
Features
• Very high performance, low cost
• Adaptive comb-based decoding
• Multiple pin-compatible versions
• Internal digital linestores
• Supports field- and frame-based decoding
• Multiple input formats
• Multiple output formats
• 10-18 Mpps data rate
• Parallel and serial control interface
• Single +5V power supply
Applications
• Studio television equipment
• Personal computer video input
• MPEG and JPEG compression inputs
Block Diagram
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
TMC22x5y
Multistandard Digital Video Decoder
Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
MASTER
VIDEOA
VIDEOB
- 3-line, 2-line, and band-split
- 8- and 10-bit processing
- CCIR-601/624 (D1), D2, CVBS, YC
- CCIR-601/624 (D1), RGB, YC
BUFFER
HSYNC
CLOCK
VSYNC
LDV
1-0
9-0
9-0
Processor
Sync Pulse
Generator
Input
Internal
B
Linestore2
Linestore1
C
R
A 1-0
Parallel Control
R/W
Y/C Split0
Y/C Split1
Y/C Split2
CS
D 7-0
Adaptive
Comb
Filter
Description
The TMC22x5y family of Digital Video Decoders offers
unprecedented, broadcast-quality video processing perfor-
mance in a single chip. It accepts line-locked or subcarrier-
locked composite, YC, or D1 digital video and produces dig-
ital components in a variety of formats.
An internal three-line adaptive comb decoder structure pro-
duces optimal picture quality with a wide range of source
material. Field- and frame-based decoding is supported with
external memory. Full comb programmability allows the
user to tailor the decoder’s response to a particular systems
goals.
A family of products offers 3-line, 2-line, and simple decod-
ers in 8-bit and 10-bit versions—all in a pin and software-
compatible format. Serial and parallel control ports are pro-
vided. These submicron CMOS devices are packaged in a
100-lead Metric Quad Flat Pack (MQFP).
SET
Global Control
RESET
Comb
Chroma
Demod
Fail
SER
Locked
SA
Burst
Loop
Serial Control
2-0
www.fairchildsemi.com
SDA
Processor
Output
SCL
Rev. 0.9.1
65-22x5y-01
G/Y
B/Cb
R/Cr
FID
AVOUT
DHSYNC
DVSYNC
2-0
9-0
9-0
9-0

Related parts for TMC22152KHC

TMC22152KHC Summary of contents

Page 1

... Generator VSYNC PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. Description The TMC22x5y family of Digital Video Decoders offers unprecedented, broadcast-quality video processing perfor- mance in a single chip ...

Page 2

TMC22x5y Table of Contents Features ......................................................................1 Applications ...............................................................1 Description .................................................................1 Block Diagram ............................................................1 Contents .....................................................................2 List of Tables and Figures ........................................3 General Description ...................................................4 Input Processor...............................................................4 Adaptive Comb Filter.....................................................4 Output Processor ............................................................5 Parallel and Serial Microprocessor Interfaces................5 Pin Assignments ........................................................5 ...

Page 3

PRODUCT SPECIFICATION List of Tables and Figures Table 1. TMC22x5y Decoder Family.................... 3 Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates....... 43 Table 3. Comb Filter Architecture ..................... 47 Table 4. Simple Example of an Adaptive ...

Page 4

TMC22x5y General Description The TMC22x5y digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format. The digital comb filter decoder implements ...

Page 5

PRODUCT SPECIFICATION processed as chrominance to find the magnitude and phase of the chrominance vector. These three components are then compared across the (0H & 1H) and (1H & 2H) taps of the comb filter to produce the difference in ...

Page 6

TMC22x5y Pin Descriptions Pin Name Pin Number Value Inputs VIDEOA 86, 85, 84, 83, TTL 9-0 82, 81, 80, 79, 78, 77 VIDEOB 75, 74, 73, 72, TTL 9-0 71, 70, 69, 68, 67, 66 VSYNC 49 TTL HSYNC 48 ...

Page 7

PRODUCT SPECIFICATION Pin Descriptions (cont.) Pin Name Pin Number Value AVOUT 30 FID 33, 32, 31 2-0 mP Interface D 45, 44, 43, 42, 7-0 41, 38, 37 63 R/W 61 RESET 51 SER ...

Page 8

TMC22x5y Control Register Map The TMC22x5y is initialized and controlled by a set of regis- ters which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line ...

Page 9

PRODUCT SPECIFICATION Reg Bit Name 0C 3-0 COMB Comb filter architecture 0D 7-6 CEST Chroma error signal transform 0D 5 CESG Chroma error signal gain 0D 4 YESG Luma error signal gain 0D 3 CESTBY Chroma error signal bypass 0D ...

Page 10

TMC22x5y Reg Bit Name Video Measurement 30 7 set to zero 30 6 LGF Line grab flag 30 5 LGEN Line grab enable 30 4 LGEXT Ext line grab enable 30 3 reserved, set to zero 30 2 PGG Pixel ...

Page 11

PRODUCT SPECIFICATION Control Register Definitions Global Control Register (00 SRST HRST Reg Bit Name 00 7 SRST 00 6 HRST 00 5-3 SET 00 2 DHVEN 00 1-0 STD SET Description Software reset. When LOW, ...

Page 12

TMC22x5y Control Register Definitions Input Processor Control (01 Reserved IPMUX IP8B Reg Bit Name 01 7 Reserved 01 6 IPMUX 01 5 IP8B 01 4 TDEN 01 3 TBLK 01 2 IPCMSB 01 1 ABMUX 01 0 CKSEL ...

Page 13

PRODUCT SPECIFICATION Control Register Definitions Burst Loop Control (02 Reserved VIPEN Reg Bit Name 02 7 Reserved 02 6 VIPEN 02 5-4 LOCK 02 3 BLM 02 2 KILD 02 1 DMODBY 02 0 CINT (continued) 4 ...

Page 14

TMC22x5y Control Register Definitions Chroma Processor Control (03 BLFS Reg Bit Name 03 7-5 BLFS 03 4 CCEN 03 3-2 CCOR 03 1 GAUBY 03 0 GAUSEL 14 (continued CCEN CCOR Description Burst loop filter ...

Page 15

PRODUCT SPECIFICATION Control Register Definitions Burst Threshold (04 Reg Bit Name 04 7-0 BTH Pedestal (05 Reg Bit Name 05 7-0 PED Luma Processor Control (06 Reserved ANEN Reg Bit Name ...

Page 16

TMC22x5y Control Register Definitions Comb Processor Control (07 LS1BY LS1IN LS2DLY Reg Bit Name 07 7 LS1BY 07 6 LS1IN 07 5 LS2DLY 07 4 SPLIT 07 3 BSFBY 07 2 BSFSEL 07 1 BSFMSB 07 0 ...

Page 17

PRODUCT SPECIFICATION Control Register Definitions Extended DRS (09 PCKF Reg Bit Name 09 7-4 PCKF 09 3-0 VSTD (continued Description Clock rate. PCKF 0000 13.50 MHz 0001 reserved 0010 reserved 0011 reserved 0100 14.32 MHz ...

Page 18

TMC22x5y Control Register Definitions Output Control (0A OP8B OPLMT OPLMT Reg Bit Name 0A 7 OP8B 0A 6-5 OPLMT 0A 4-3 MSEN 0A 2 OPCMSB 0A 1 YBAL 0A 0 BUREN Notes enable “super blacks” ...

Page 19

PRODUCT SPECIFICATION Control Register Definitions Output Control (0B FMT422 CDEC YUVT Reg Bit Name 0B 7 FMT422 0B 6 CDEC 0B 5 YUVT 0B 4-2 Reserved 0B 1 DRSEN 0B 0 DRSCK (continued Reserved Description ...

Page 20

TMC22x5y Control Register Definitions Comb Filter Control (0C ADAPT YCES Reg Bit Name 0C 7-6 ADAPT 0C 5 YCES 0C 4 YCSEL 0C 3-0 COMB 20 (continued YCSEL Description Adaption mode. Sets the 3-line comb ...

Page 21

PRODUCT SPECIFICATION Control Register Definitions Comb Filter Control (0D CEST CESG Reg Bit Name 0D 7-6 CEST 0D 5 CESG 0D 4 YESG 0D 3 CESTBY 0D 2 XFEN 0D 1 FAST 0D 0 YWBY (continued ...

Page 22

TMC22x5y Control Register Definitions Comb Filter Control (0E XIP Reg Bit Name 0E 7-6 XIP 0E 5-4 XSF 0E 3-2 YMUX 0E 1-0 CMUX 22 (continued XSF YMUX Description XLUT input select. Selects the comb ...

Page 23

PRODUCT SPECIFICATION Control Register Definitions Comb Filter Control (0F Reserved CAT Reg Bit Name Description 0F 7 Reserved Reserved, set to zero. 0F 6-5 CAT Adaption threshold. Fixes threshold at which different comb filters are selected. 0F ...

Page 24

TMC22x5y Control Register Definitions Sync Pulse Generator (11 Reg Bit Name 11 7-0 STB Sync Pulse Generator (12 Reg Bit Name 12 7-0 BTV Sync Pulse Generator (13 Reg ...

Page 25

PRODUCT SPECIFICATION Control Register Definitions Sync Pulse Generator (15 Reserved Reg Bit Name 15 7 Reserved 15 6-2 VINDO 15 1 VDIV 15 0 VDOV Sync Pulse Generator (16 Reserved Reg Bit Name 16 ...

Page 26

TMC22x5y Control Register Definitions Buffered register set 0 (17) Active when BUFFER pin set LOW SG0 SG0 SG0 7 6 Reg Bit Name 17 7-0 SG0 7-0 Buffered register set 0 (18) Active when BUFFER pin set ...

Page 27

PRODUCT SPECIFICATION Control Register Definitions Buffered register set 0 (1C) Active when BUFFER pin set LOW YOFF0 YOFF0 YOFF0 7 6 Reg Bit Name 1C 7-0 YOFF0 7-0 Buffered register set 0 (1D) Active when BUFFER pin set ...

Page 28

TMC22x5y Control Register Definitions Normalized Subcarrier Frequency (21 FSC FSC FSC 11 10 Reg Bit Name 21 7-0 FSC 11-4 Normalized Subcarrier Frequency (22 FSC FSC FSC 19 18 Reg Bit Name 22 7-0 ...

Page 29

PRODUCT SPECIFICATION Control Register Definitions Output Format Control (26 Reserved LDVIO Reg Bit Name 26 7-6 Reserved 26 5 LDVIO 26 4 OPCKS 26 3 DPCEN 26 2-0 DPC Buffered register set 1 (27) Active when BUFFER ...

Page 30

TMC22x5y Control Register Definitions Buffered register set 1 (29) Active when BUFFER pin set HIGH UG1 UG1 UG1 7 6 Reg Bit Name 29 7-0 UG1 7-0 Buffered register set 1 (2A) Active when BUFFER pin set ...

Page 31

PRODUCT SPECIFICATION Control Register Definitions Buffered register set 1 (2D) Active when BUFFER pin set HIGH Reserved Reg Bit Name 2D 7-3 Reserved 2D 2 YOFF1 8 2D 1-0 SG1 7,0 Buffered register set 1 (2E) Active ...

Page 32

TMC22x5y Control Register Definitions Video Measurement (30 Reserved LGF LGEN Reg Bit Name 30 7 Reserved 30 6 LGF 30 5 LGEN 30 4 LGEXT 30 3 Reserved 30 2 PGG 30 1 PGEN 30 0 PGEXT ...

Page 33

PRODUCT SPECIFICATION Control Register Definitions Video Measurement (33 Reserved FG Reg Bit Name 33 7 Reserved 33 6 2-0 PG 10-8 Registers 34-3C are Read-Only Register (34 ...

Page 34

TMC22x5y Control Register Definitions Register (38 Reg Bit Name 38 7-0 Y 9-2 Register (39 Reg Bit Name 39 7-0 M 9-2 Register (3A) ...

Page 35

PRODUCT SPECIFICATION Control Register Definitions Test Control (3D-3F Reg Bit Name 3D-3F 7-0 TEST Status - Read Only (40 Reg Bit Name 40 7-0 DDSPH Status - Read Only (41 LINEST ...

Page 36

TMC22x5y Control Register Definitions Status - Read Only (43 YGO YGU UBO Reg Bit Name 43 7 YGO 43 6 YGU 43 5 UBO 43 4 UBU 43 3 VRO 43 2 VRU 43 1-0 Reserved Status ...

Page 37

PRODUCT SPECIFICATION Control Register Definitions Status - Read Only (47 Reg Bit Name 47 7-0 REVID Status - Read Only (48-4A Reg Bit Name 48-4A 7-0 Reserved Status - Read Only (4B ...

Page 38

TMC22x5y Decoder Introduction All composite video decoders perform fundamentally the same operation. The first stage is to separate the luminance and chrominance. The second stage is to lock the internally generated sine and cosine waveforms to the burst on the ...

Page 39

PRODUCT SPECIFICATION Notch Filter Amplitude Chrominance (dB) Subcarrier 0 -3 Luminance Chrominance (& High Frequency Luminance) -20 F Figure 5. Examples of Notch and Bandpass Filters centered at the subcarrier frequency produces the chroma signal. This simple technique works well ...

Page 40

TMC22x5y phase relationship to the chroma on 1H. Therefore normally 0H and 2H are added together to produce the average luma across 3 lines and this is then subtracted from 1H to produce the combed chroma. FIELD LINE no PAL ...

Page 41

PRODUCT SPECIFICATION LINE no FIELD 1 FIELD (F0H) U 336 (0H) U 337 338 Figure 9. Chrominance Vector Rotation Over 4 ...

Page 42

TMC22x5y The TMC22x5y Comb Filter Architecture The TMC22x5y, when implementing a line based comb filter, has a core architecture as shown in Figure 10. The con- cept of the complementary bandsplit filter is also observed in the complementary comb filter ...

Page 43

PRODUCT SPECIFICATION TMC22x5y Functional Description Input Processor The input processor selects between the two external video sources on VIDEO A and VIDEO B. If the TRS stripper or GRS stacker is active, then the user must select the input with ...

Page 44

TMC22x5y 0 -10 -20 Bandsplit Filter 2 -30 -40 Bandsplit Filter 1 -50 -60 -70 Normalized Frequency Figure 13. Bandsplit Filter, Full Frequency Response Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates F SC Pixel Rate ...

Page 45

PRODUCT SPECIFICATION Primary LPF Input BSFSEL 2:1 MUX Secondary Input LS1IN The primary and secondary inputs are selected within the input processor. The primary input is normally the undelayed composite video signal in line, field, and frame based comb filters ...

Page 46

TMC22x5y Adaptive Comb Filter The IPCF[1:0] register bits select the inputs to the adaptive comb filter, this would normally be xHH for chroma combs, xHF for luma combs, and xHL if the luminance signal was to be sampled dropped on ...

Page 47

PRODUCT SPECIFICATION The comb filter architecture performs chrominance or lumi- nance comb filtering on PAL or NTSC video signals, by implementing one of sixteen independent chroma and luma comb filter algorithms. The highest level of the adaptive comb filter configuration ...

Page 48

TMC22x5y In either of these methods, the “K” signal can be used to cross fade between the YCOMB and the SIMPLE bandsplit signals. The resulting comb filter equation can be expressed as: + Combed Luma = Simple (K * Combed ...

Page 49

PRODUCT SPECIFICATION Generation of the Comb Fail Signals Luma Error Signals The signals from the 3 low pass filters, 0HL, 1HL, and 2HL are subtracted from one another to produce an error signal proportional to the luma comb fail. The ...

Page 50

TMC22x5y ADAPT[1:0] UYE LYE Comb UPE Fail LPE Logic UME LME STA[3:0] line comb to switch directly to simple. The switching between these two comb architectures is independent of the mix signal, K. For 3-line Y/C comb filters, an external ...

Page 51

PRODUCT SPECIFICATION YERR XLUT X[7:0] Input PERR Select MERR XIP[1:0] For PAL comb filters the LYE, LME, and LPE errors signals are always selected by default. In this way the error signals into the XLUT always represent the comb filter ...

Page 52

TMC22x5y . – Chrominance Burst Locked Loop Figure 21. Block Diagram of Digital Burst Locked Loop Digital Burst Locked Loop The digital burst locked loop provides sine and cosine signals which are phase locked to the incoming burst signal. These ...

Page 53

PRODUCT SPECIFICATION Table 10. PAL-M Bruch Blanking Sequence Internal Burst Internal line # present frame # 258 Yes 259 Yes 1 or ...

Page 54

TMC22x5y Output Processor Mixed Sync – – Y Data VIDEOB PED[7:0] LPF Clamp Circuit 256 240 CLMP MSIP [1: Data UGx[10: Data VGx[10:0] Clamp Circuit A clamp pulse generated by the Burst Gate signal is used ...

Page 55

PRODUCT SPECIFICATION If either of the error signals indicates that the magnitude difference is above the programmed threshold ANEN is LOW, the adaptive notch filter is bypassed. The output of the adaptive notch filter is rounded to 8 ...

Page 56

TMC22x5y Y Offset The 8 bit Y offset adds any offset required in the Y or RGB data outputs. For example 64 (16) for the 64 (16) to 940 (235) 10 bit (8 bit) 601 outputs. When the output is ...

Page 57

PRODUCT SPECIFICATION Simple Luma Color Correction If the YBAL register bit is set HIGH, and the luma data reaches or exceeds the luma limits, there should data at that time; therefore the color data are ...

Page 58

TMC22x5y Sync Pulse Generator The vertical and horizontal references to the decoder can be from external VSYNC and HSYNC pulses, decoded from TRS and TRS-ID words, or from the internal sync separator which extracts the sync information from the digitized ...

Page 59

PRODUCT SPECIFICATION DHSYNC are referenced to the input data (0HFLAT) and not the output of the LSTORE1, i.e. 1HFLAT. The duration of the DVSYNC signal is fixed to one line and the duration of the DHSYNC signal is 64 clock ...

Page 60

TMC22x5y Table 20. Table of Line Idents, LID[4:0] Line no: 260 & 261 262 263 - 307 308 309 310 311 312 Timing Parameters Subcarrier Programming The color subcarrier is produced by an internal 28 bit Direct Digital Synthesizer (DDS) ...

Page 61

PRODUCT SPECIFICATION Vertical Blanking 256 257 FIELDS 1 AND 3 258 259 260 UVV UVV HSYNC VSYNC FLD 258 259 FIELDS 2 AND 4 260 261 UVV UVE EE EE HSYNC VSYNC FLD ...

Page 62

TMC22x5y 309 310 FIELDS 1 AND 5 311 312 0 UVV - HSYNC VSYNC FLD 308 309 FIELDS 2 AND 6 310 311 UVV - HSYNC VSYNC FLD 309 310 FIELDS 3 AND 7 ...

Page 63

PRODUCT SPECIFICATION 258 259 260 261 262 UVV UVV HSYNC VSYNC FLD 258 259 260 261 UVV - HSYNC VSYNC FLD 258 259 260 261 262 UVV - HSYNC VSYNC FLD 259 ...

Page 64

TMC22x5y VINDO Operation The VINDO circuit uses the line idents on LID blanking signals to control the comb filter output and the blanking of the YUV data in the output matrix during the vertical blanking period. The vertical window VINDO ...

Page 65

PRODUCT SPECIFICATION Table 23. Pixel Grab Control LGEXT PGEN PGEXT LGEN single pixel every ...

Page 66

TMC22x5y Examples: NTSC std with STS programmed to 858. Base pixels per quadrant = Int(858/4) = 214 Pixel 0: 1. Pixel 0 <= 4*Int(858/4) 2. Required pixel 0 < 214 therefore quadrant = 0, [PG[10:9] = 00] 3. PG[10:0] = ...

Page 67

PRODUCT SPECIFICATION R/W ADR D 7-0 Figure 33. Microprocessor Parallel Port – Write Timing R/W ADR D 7-0 Figure 34. Microprocessor Parallel Port – Read Timing Serial Control Port (R-Bus) In addition to the ...

Page 68

TMC22x5y Table 25. Serial Port Addresses bit 7 bit 6 bit 5 bit 4 bit (MSB) ( ...

Page 69

PRODUCT SPECIFICATION • Start signal • Slave Address byte (R/W bit = HIGH) • Data byte from base address • Stop signal Read from four consecutive control registers • Start signal • Slave Address byte (R/W bit = LOW) • ...

Page 70

TMC22x5y Equivalent Circuits and Threshold Levels Digital Input GND Figure 37. Equivalent Digital Input Circuit SET or RESET Three-State Outputs 27014B Figure 38. Equivalent Digital Output t DIS 0.5V 0.5V Figure 39. Threshold Levels for ...

Page 71

PRODUCT SPECIFICATION Absolute Maximum Ratings Parameter Power Supply voltage Digital Inputs Applied Voltage 3, 4 Forced current Digital Outputs 2 Applied voltage 3, 4 Forced current Short circuit duration (single output in HIGH state to ground) Analog Output Short circuit ...

Page 72

TMC22x5y Operating Conditions Parameter V Power Supply Voltage DD V Input Voltage, Logic HIGH IH TTL Compatible Inputs Serial Port (SDA and SCL) V Input Voltage, Logic LOW IL TTL Compatible Inputs Serial Port (SDA and SCL) I Output Current, ...

Page 73

PRODUCT SPECIFICATION Operating Conditions (continued) Parameter Pixel Interface (output) t CLOCK to DHSYNC and DVYSNC, AVOUT, and FID POD Time t CLOCK to data, Propagation Time POD t Int. or Ext. LDV to data, Propagation Time POD t Clock to ...

Page 74

TMC22x5y Operating Conditions (continued) Parameter Parallel Microprocessor Interface t CS Pulse Width, LOW PWLCS t CS Pulse Width, HIGH PWHCS t Address Setup Time SA t Address Hold Time HA t Data Setup Time (write Data Hold Time ...

Page 75

PRODUCT SPECIFICATION Switching Characteristics Parameter t Output Delay low-Z DOZ t Output Hold Time high-Z HOM t Output Delay Data Valid DOM Note: Timing reference points are at the 50% level, digital output load ...

Page 76

TMC22x5y Programming Examples Standard: NTSC-M Mode: Line-Locked Input Format: 13.5 Composite Output Format: RGB (0-1023) Sync on Green Decoder: Adaptive 3-Line Chroma Comb Filter Register Map ...

Page 77

PRODUCT SPECIFICATION Programming Examples Standard: NTSC Mode: Line-Locked Input Format: 13.5 MHz Composite Video Output Format: YUV Decoder: Adaptive 3-Line Comb Register Map ...

Page 78

TMC22x5y Programming Examples Standard: PAL Mode: Line-Locked Input Format: PAL-YC Output Format: Y, Cb, Cr (D1 Out) Decoder: Register Map: No Comb ...

Page 79

PRODUCT SPECIFICATION Programming Examples Standard: NTSC-M Mode: D1 Mode Input Format: D1 [Y] Multiplexed Data w/TRS B R Output Format Output DHSync + DVSync B R Decoder: Simple Transcoder Register Map ...

Page 80

TMC22x5y Programming Worksheet Standard: Mode: Input Format: Output Format: Decoder: Register Map The DRS appears on the output at the Bandsplit Filter 0 -10 -20 Bandsplit Filter 2 -30 -40 Bandsplit Filter 1 ...

Page 81

PRODUCT SPECIFICATION Related Products • TMC22071 Genlocking Video Digitizer • TMC22x9x Digital Video Encoders • TMC2081 Digital Video Mixer • TMC3003 Triple 10-bit D/A Converter TMC22x5y 81 ...

Page 82

TMC22x5y Notes: 82 PRODUCT SPECIFICATION ...

Page 83

PRODUCT SPECIFICATION Mechanical Dimensions – 100 Lead MQFP Package Inches Millimeters Symbol Min. Max. Min. Max. A — .134 — 3.40 A1 .010 — .25 A2 .100 .120 2.55 3.05 .015 B .009 .23 C .005 .009 .13 D .904 ...

Page 84

... TMC22052KHC 0°C to 70°C TMC22053KHC 0°C to 70°C TMC22151KHC 0°C to 70°C TMC22152KHC 0°C to 70°C TMC22153KHC 0°C to 70°C LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION ...

Related keywords