MT47H64M16HR-25E:H Micron Technology Inc, MT47H64M16HR-25E:H Datasheet - Page 103

no-image

MT47H64M16HR-25E:H

Manufacturer Part Number
MT47H64M16HR-25E:H
Description
64MX16 DDR2 SDRAM PLASTIC PBF FBGA 1.8V
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet

Specifications of MT47H64M16HR-25E:H

Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
160mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-TFBGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H64M16HR-25E:H
Manufacturer:
MICRON
Quantity:
11 200
Part Number:
MT47H64M16HR-25E:H
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT47H64M16HR-25E:H
Manufacturer:
MICRON44
Quantity:
66
Part Number:
MT47H64M16HR-25E:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H64M16HR-25E:H
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT47H64M16HR-25E:H
Quantity:
7 000
Part Number:
MT47H64M16HR-25E:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 55: x16 Data Output Timing –
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQ8–DQ15 and UDQS collectively 6
DQ0–DQ7 and LDQS collectively 6
DQ (first data no longer valid) 4
DQ (first data no longer valid) 4
DQ (first data no longer valid) 7
DQ (first data no longer valid) 7
DQ (last data valid) 4
DQ (last data valid) 4
DQ (last data valid) 7
DQ (last data valid) 7
Notes:
UDQS#
UDQS 3
LDSQ#
LDQS 3
1.
2.
3. DQ transitioning after the DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
CK#
CK
t
t
transitions, and ends with the last valid transition of DQ.
lower byte, and UDQS defines the upper byte.
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
T1
t HP 1
t
DQSQ,
t HP 1
t
CL or
t DQSQ 2
t
t QH 5
QH, and Data Valid Window
t DQSQ 2
T2
t QH 5
Data valid
t
window
103
CH clock transitions collectively when a bank is active.
Data valid
T2
T2
T2
t HP 1
window
T2
T2
T2
t DQSQ 2
t QHS
T2n
t QH 5
t DQSQ 2
t QHS
t QH 5
Data valid
window
t HP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2n
T2n
T2n
Data valid
window
T2n
T2n
T2n
T3
t DQSQ 2
t QHS
t QH 5
1Gb: x4, x8, x16 DDR2 SDRAM
t QHS
t DQSQ 2
t QH 5
t HP 1
Data valid
window
Data valid
window
T3
T3
T3
T3
T3n
T3
T3
t
DQSQ window. LDQS defines the
t DQSQ 2
t DQSQ 2
t QHS
t QHS
t HP 1
t QH 5
t QH 5
Data valid
window
Data valid
© 2004 Micron Technology, Inc. All rights reserved.
window
T3n
T4
T3n
T3n
T3n
T3n
T3n
t QHS
t QHS
READ

Related parts for MT47H64M16HR-25E:H