MT47H64M16HR-25E:H Micron Technology Inc, MT47H64M16HR-25E:H Datasheet - Page 64

• Manufacturer Part Number: MT47H64M16HR-25E:H
• Description: 64MX16 DDR2 SDRAM PLASTIC PBF FBGA 1.8V
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr
• Series: -r

Specifications of MT47H64M16HR-25E:H

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 160mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Lead Free Status / Rohs Status: Compliant

Table 32: DDR2-667/800/1066
All units are shown in picoseconds
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQ
Slew
Rate
(V/ns)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
–100 –188 –100 –188 –100 –188
t
100
–13
–22
–34
–60
67
2.8 V/ns
DS
–5
Δ
0
–125
t
–14
–31
–54
–83
DH
63
42
Δ
0
t
100
–13
–22
–34
–60
Notes:
67
2.4 V/ns
DS
–5
Δ
0
–125
t
–14
–31
–54
–83
DH
63
42
Δ
0
1. For all input signals the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be ob-
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 33 (page 65) are the
sheet value to the derating value listed in Table 32.
t
crossing of V
signal is defined as the slew rate between the last crossing of V
ing of V
between the shaded “V
value (see Figure 27 (page 67)). If the actual signal is later than the nominal slew rate
line anywhere between shaded “V
to the actual signal from the AC level to DC level is used for the derating value (see Fig-
ure 28 (page 67)).
t
crossing of V
signal is defined as the slew rate between the last crossing of V
ing of V
between the shaded “DC level to V
rating value (see Figure 29 (page 68)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded “DC to V
tangent line to the actual signal from the DC level to V
ing value (see Figure 30 (page 68)).
will not have reached V
put signal is still required to complete the transition and reach V
tained by linear interpolation.
characterization.
DQS single-ended slew rate derating with DQS referenced at V
the logic levels
to the AC/DC trip points to DQ referenced to V
ble 34 provides the V
t
100
–13
–22
–34
–60
DS nominal slew rate for a rising signal is defined as the slew rate between the last
DH nominal slew rate for a rising signal is defined as the slew rate between the last
DS
67
–5
2.0 V/ns
Δ
0
t
DS,
–125
t
–14
–31
–54
–83
t
DH
63
42
Δ
DH Derating Values with Differential Strobe
0
IL(AC)max
REF(DC)
DQS, DQS# Differential Slew Rate
REF(DC)
IL(DC)max
t
112
–10
–22
–48
–88
79
12
1.8 V/ns
DS
–1
. If the actual signal is always later than the nominal slew rate line
Δ
7
t
. If the actual signal is always earlier than the nominal slew rate line
DS
b
–113
–176
t
and the first crossing of V
–19
–42
–71
DH
75
54
12
–2
and
Δ
and the first crossing of V
REF
IH[AC]
REF(DC)
-based fully derated values for the DQ (
t
DH
t
64
124
–10
–36
–76
91
24
19
11
1.6 V/ns
DS
Δ
2
b
/V
t
. Converting the derated base values from DQ referenced
DS and
to AC region,” use the nominal slew rate for the derating
IL[AC]
–101
–164
t
–30
–59
DH
87
66
24
10
–7
Δ
REF(DC)
REF(DC)
at the time of the rising clock transition), a valid in-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DH required is calculated by adding the data
t
136
103
–24
–64
1.4 V/ns
DS
36
31
23
14
Δ
2
to AC region,” the slew rate of a tangent line
region,” use the nominal slew rate for the de-
1Gb: x4, x8, x16 DDR2 SDRAM
–152
IH(AC)min
t
–18
–47
–89
DH
99
78
36
22
Δ
5
REF(DC)
REF
is listed in Table 34 (page 65). Ta-
Input Slew Rate Derating
t
148
115
–12
–52
48
43
35
26
14
1.2 V/ns
DS
.
.
Δ
t
t
DH nominal slew rate for a falling
REF(DC)
DS nominal slew rate for a falling
REF(DC)
–140
t
111
–35
–77
DH
90
48
34
17
–6
Δ
© 2004 Micron Technology, Inc. All rights reserved.
region,” the slew rate of a
level is used for the derat-
IH(DC)min
REF
REF(DC)
t
DS
t
160
127
–40
IH(AC)
DS
60
55
47
38
26
1.0 V/ns
Δ
0
and DQ referenced at
a
and
/V
and the first cross-
–128
and the first cross-
t
123
102
–23
–65
DH
60
46
29
IL(AC)
Δ
6
t
DH
.
a
) for
t
172
139
–28
DS
72
67
59
50
38
12
0.8 V/ns
Δ
–116
t
135
114
–11
–53
DH
72
58
41
18
Δ